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參數(shù)資料
| 型號： | XA3SD3400A-4FGG676I |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 39/58頁 |
| 文件大?。?/td> | 0K |
| 描述： | SPARTAN-3ADSP FPGA 3400K 676FBGA |
| 產(chǎn)品培訓模塊： | Extended Spartan 3A FPGA Family |
| 標準包裝： | 40 |
| 系列： | Spartan®-3A DSP XA |
| LAB/CLB數(shù)： | 5968 |
| 邏輯元件/單元數(shù)： | 53712 |
| RAM 位總計： | 2322432 |
| 輸入/輸出數(shù)： | 469 |
| 門數(shù)： | 3400000 |
| 電源電壓： | 1.14 V ~ 1.26 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 676-BGA |
| 供應商設備封裝： | 676-FBGA（27x27） |
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XA Spartan-3A DSP Automotive FPGA Family Data Sheet
DS705 (v2.0) April 18, 2011
Product Specification
44
Digital Frequency Synthesizer
Table 39: Recommended Operating Conditions for the DFS
Symbol
Description
Speed Grade: -4
Units
Min
Max
Input Frequency Ranges(2)
FCLKIN
CLKIN_FREQ_FX
Frequency for the CLKIN input
0.200
333
MHz
Input Clock Jitter Tolerance(3)
CLKIN_CYC_JITT_FX_LF
Cycle-to-cycle jitter at the CLKIN input,
based on CLKFX output frequency
FCLKFX 150 MHz
–±300
ps
CLKIN_CYC_JITT_FX_HF
FCLKFX 150 MHz
–±150
ps
CLKIN_PER_JITT_FX
Period jitter at the CLKIN input
–±1
ns
Notes:
1.
DFS specifications apply when either of the DFS outputs (CLKFX or CLKFX180) is used.
2.
If both DFS and DLL outputs are used on the same DCM, follow the more restrictive CLKIN_FREQ_DLL specifications in Table 37.
3.
CLKIN input jitter beyond these limits may cause the DCM to lose lock.
4.
The DCM specifications are guaranteed when both adjacent DCMs are locked.
Table 40: Switching Characteristics for the DFS
Symbol
Description
Device
Speed Grade: -4
Units
Min
Max
Output Frequency Ranges
CLKOUT_FREQ_FX(2)
Frequency for the CLKFX and CLKFX180 outputs
All
5
311
MHz
Output Clock Jitter(3,4)
CLKOUT_PER_JITT_FX
Period jitter at the CLKFX and CLKFX180
outputs.
Typ
Max
CLKIN
20 MHz
All
Use the Spartan-3A
Jitter Calculator:
ps
CLKIN
20 MHz
±[1% of
CLKFX
period
+ 100]
±[1% of
CLKFX
period
+ 200]
ps
Duty Cycle(5,6)
CLKOUT_DUTY_CYCLE_FX Duty cycle precision for the CLKFX and CLKFX180 outputs,
including the BUFGMUX and clock tree duty-cycle distortion
All
–
±[1% of
CLKFX period
+ 350]
ps
Phase Alignment(6)
CLKOUT_PHASE_FX
Phase offset between the DFS CLKFX output and the DLL
CLK0 output when both the DFS and DLL are used
All
–
±200
ps
CLKOUT_PHASE_FX180
Phase offset between the DFS CLKFX180 output and the
DLL CLK0 output when both the DFS and DLL are used
All
–
±[1% of
CLKFX period
+ 200]
ps
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