參數(shù)資料
型號(hào): XA3SD3400A-4FGG676I
廠商: Xilinx Inc
文件頁數(shù): 41/58頁
文件大?。?/td> 0K
描述: SPARTAN-3ADSP FPGA 3400K 676FBGA
產(chǎn)品培訓(xùn)模塊: Extended Spartan 3A FPGA Family
標(biāo)準(zhǔn)包裝: 40
系列: Spartan®-3A DSP XA
LAB/CLB數(shù): 5968
邏輯元件/單元數(shù): 53712
RAM 位總計(jì): 2322432
輸入/輸出數(shù): 469
門數(shù): 3400000
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 676-BGA
供應(yīng)商設(shè)備封裝: 676-FBGA(27x27)
XA Spartan-3A DSP Automotive FPGA Family Data Sheet
DS705 (v2.0) April 18, 2011
Product Specification
46
Miscellaneous DCM Timing
DNA Port Timing
Table 43: Miscellaneous DCM Timing
Symbol
Description
Min
Max
Units
DCM_RST_PW_MIN
Minimum duration of a RST pulse width
3
–CLKIN
cycles
Table 44: DNA_PORT Interface Timing
Symbol
Description
Min
Max
Units
TDNASSU
Setup time on SHIFT before the rising edge of CLK
1.0
–ns
TDNASH
Hold time on SHIFT after the rising edge of CLK
0.5
–ns
TDNADSU
Setup time on DIN before the rising edge of CLK
1.0
–ns
TDNADH
Hold time on DIN after the rising edge of CLK
0.5
–ns
TDNARSU
Setup time on READ before the rising edge of CLK
5.0
10,000
ns
TDNARH
Hold time on READ after the rising edge of CLK
0.0
–ns
TDNADCKO
Clock-to-output delay on DOUT after rising edge of CLK
0.5
1.5
ns
TDNACLKF
CLK frequency
0.0
100
MHz
TDNACLKH
CLK High time
1.0
ns
TDNACLKL
CLK Low time
1.0
ns
Notes:
1.
The minimum READ pulse width is 5 ns, and the maximum READ pulse width is 10 s.
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