參數(shù)資料
型號(hào)： XA3SD3400A-4FGG676I
廠商： Xilinx Inc
文件頁數(shù)： 33/58頁
文件大小： 0K
描述： SPARTAN-3ADSP FPGA 3400K 676FBGA
產(chǎn)品培訓(xùn)模塊： Extended Spartan 3A FPGA Family
標(biāo)準(zhǔn)包裝： 40
系列： Spartan®-3A DSP XA
LAB/CLB數(shù)： 5968
邏輯元件/單元數(shù)： 53712
RAM 位總計(jì)： 2322432
輸入/輸出數(shù)： 469
門數(shù)： 3400000
電源電壓： 1.14 V ~ 1.26 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 676-BGA
供應(yīng)商設(shè)備封裝： 676-FBGA（27x27）
XA Spartan-3A DSP Automotive FPGA Family Data Sheet
DS705 (v2.0) April 18, 2011
Product Specification
39
Block RAM Timing
Table 34: Block RAM Timing
Symbol
Description
Speed Grade: -4
Units
Min
Max
Clock-to-Output Times
TRCKO_DOA_NC
When reading from block RAM, the delay from the active transition at the CLK
input to data appearing at the DOUT output
–2.80
ns
TRCKO_DOA
Clock CLK to DOUT output (with output register)
–1.45
ns
Setup Times
TRCCK_ADDR
Setup time for the ADDR inputs before the active transition at the CLK input
of the block RAM
0.46
–ns
TRDCK_DIB
Setup time for data at the DIN inputs before the active transition at the CLK
input of the block RAM
0.33
–ns
TRCCK_ENB
Setup time for the EN input before the active transition at the CLK input of the
block RAM
0.60
–ns
TRCCK_WEB
Setup time for the WE input before the active transition at the CLK input of the
block RAM
0.75
–ns
TRCCK_REGCE
Setup time for the CE input before the active transition at the CLK input of the
block RAM
0.40
–ns
TRCCK_RST
Setup time for the RST input before the active transition at the CLK input of
the block RAM
0.25
–ns
Hold Times
TRCKC_ADDR
Hold time on the ADDR inputs after the active transition at the CLK input
0.10
–ns
TRDCK_DIB
Hold time on the DIN inputs after the active transition at the CLK input
0.10
–ns
TRCKC_ENB
Hold time on the EN input after the active transition at the CLK input
0.10
–ns
TRCKC_WEB
Hold time on the WE input after the active transition at the CLK input
0.10
–ns
TRCKC_REGCE
Hold time on the CE input after the active transition at the CLK input
0.10
–ns
TRCKC_RST
Hold time on the RST input after the active transition at the CLK input
0.10
–ns
Clock Timing
TBPWH
High pulse width of the CLK signal
1.79
–ns
TBPWL
Low pulse width of the CLK signal
1.79
–ns
Clock Frequency
FBRAM
Block RAM clock frequency
0
280
MHz
Notes:
1.
The numbers in this table are based on the operating conditions set forth in Table 8.
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