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參數(shù)資料
| 型號(hào)： | XA3SD3400A-4FGG676I |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 30/58頁 |
| 文件大?。?/td> | 0K |
| 描述： | SPARTAN-3ADSP FPGA 3400K 676FBGA |
| 產(chǎn)品培訓(xùn)模塊： | Extended Spartan 3A FPGA Family |
| 標(biāo)準(zhǔn)包裝： | 40 |
| 系列： | Spartan®-3A DSP XA |
| LAB/CLB數(shù)： | 5968 |
| 邏輯元件/單元數(shù)： | 53712 |
| RAM 位總計(jì)： | 2322432 |
| 輸入/輸出數(shù)： | 469 |
| 門數(shù)： | 3400000 |
| 電源電壓： | 1.14 V ~ 1.26 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 676-BGA |
| 供應(yīng)商設(shè)備封裝： | 676-FBGA（27x27） |
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XA Spartan-3A DSP Automotive FPGA Family Data Sheet
DS705 (v2.0) April 18, 2011
Product Specification
36
Differential Standards (Number of I/O Pairs or Channels)
LVDS_25
22
–
LVDS_33
27
–
BLVDS_25
44
MINI_LVDS_25
22
–
MINI_LVDS_33
27
–
LVPECL_25
Inputs Only
LVPECL_33
RSDS_25
22
–
RSDS_33
27
–
TMDS_33
27
–
PPDS_25
22
–
PPDS_33
27
–
DIFF_HSTL_I_18
8
DIFF_HSTL_II_18
–2
DIFF_HSTL_III_18
5
4
DIFF_HSTL_I
–10
DIFF_HSTL_III
–4
DIFF_SSTL18_I
3
7
DIFF_SSTL18_II
–1
DIFF_SSTL2_I
99
DIFF_SSTL2_II
–4
DIFF_SSTL3_I
45
DIFF_SSTL3_II
33
Notes:
1.
Not all I/O standards are supported on all I/O banks. The left and right banks (I/O banks 1 and 3) support higher output drive current than
the top and bottom banks (I/O banks 0 and 2). Similarly, true differential output standards, such as LVDS, RSDS, PPDS, miniLVDS, and
TMDS, are only supported in top or bottom banks (I/O banks 0 and 2). Refer to UG331, Spartan-3 Generation FPGA User Guide for
additional information.
2.
The numbers in this table are recommendations that assume sound board layout practice. This table assumes the following parasitic factors:
combined PCB trace and land inductance per VCCO and GND pin of 1.0 nH, receiver capacitive load of 15 pF. Test limits are the VIL/VIH
voltage limits for the respective I/O standard.
3.
If more than one signal standard is assigned to the I/Os of a given bank, refer to XAPP689, Managing Ground Bounce in Large FPGAs for
information on how to perform weighted average SSO calculations.
Table 29: Recommended Number of Simultaneously Switching Outputs per VCCO/GND Pair (VCCAUX=3.3V) (Cont’d)
Signal Standard (IOSTANDARD)
Package Type: CSG484 and FGG676
Top, Bottom (Banks 0,2)
Left, Right (Banks 1,3)
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