參數(shù)資料
型號(hào)： XA3SD3400A-4FGG676I
廠商： Xilinx Inc
文件頁(yè)數(shù)： 16/58頁(yè)
文件大?。?/td> 0K
描述： SPARTAN-3ADSP FPGA 3400K 676FBGA
產(chǎn)品培訓(xùn)模塊： Extended Spartan 3A FPGA Family
標(biāo)準(zhǔn)包裝： 40
系列： Spartan®-3A DSP XA
LAB/CLB數(shù)： 5968
邏輯元件/單元數(shù)： 53712
RAM 位總計(jì)： 2322432
輸入/輸出數(shù)： 469
門數(shù)： 3400000
電源電壓： 1.14 V ~ 1.26 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 676-BGA
供應(yīng)商設(shè)備封裝： 676-FBGA（27x27）
XA Spartan-3A DSP Automotive FPGA Family Data Sheet
DS705 (v2.0) April 18, 2011
Product Specification
23
Output Propagation Times
Three-State Output Propagation Times
Table 24: Timing for the IOB Output Path
Symbol
Description
Conditions
Device
Speed Grade: -4
Units
Max
Clock-to-Output Times
TIOCKP
When reading from the Output Flip-Flop (OFF),
the time from the active transition at the OCLK
input to data appearing at the Output pin
LVCMOS25(2), 12 mA
output drive, Fast slew
rate
All
3.13
ns
Propagation Times
TIOOP
The time it takes for data to travel from the JOB’s
O input to the Output pin
LVCMOS25(2), 12 mA
output drive, Fast slew
rate
All
2.91
ns
TIOOLP
The time it takes for data to travel from the O input
through the OFF latch to the Output pin
All
2.85
ns
Set/Reset Times
TIOSRP
Time from asserting the OFF’s SR input to
setting/resetting data at the Output pin
LVCMOS25(2), 12 mA
output drive, Fast slew
rate
All
3.89
ns
TIOGSRQ
Time from asserting the Global Set Reset (GSR)
input on the STARTUP_SPARTAN3A primitive to
setting/resetting data at the Output pin
All
9.65
ns
Notes:
1.
The numbers in this table are tested using the methodology presented in Table 27 and are based on the operating conditions set forth in
2.
This time requires adjustment whenever a signal standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data
Output. When this is true, add the appropriate Output adjustment from Table 26.
Table 25: Timing for the IOB Three-State Path
Symbol
Description
Conditions
Device
Speed Grade: -4
Units
Max
Synchronous Output Enable/Disable Times
TIOCKHZ
Time from the active transition at the OTCLK input
of the Three-state Flip-Flop (TFF) to when the
Output pin enters the high-impedance state
LVCMOS25, 12 mA
output drive, Fast slew
rate
All
1.39
ns
TIOCKON(2)
Time from the active transition at TFF’s OTCLK
input to when the Output pin drives valid data
All
3.35
ns
Asynchronous Output Enable/Disable Times
TGTS
Time from asserting the Global Three State (GTS)
input on the STARTUP_SPARTAN3A primitive to
when the Output pin enters the high-impedance
state
LVCMOS25, 12 mA
output drive, Fast slew
rate
All
10.36
ns
Set/Reset Times
TIOSRHZ
Time from asserting TFF’s SR input to when the
Output pin enters a high-impedance state
LVCMOS25, 12 mA
output drive, Fast slew
rate
All
1.86
ns
TIOSRON(2)
Time from asserting TFF’s SR input at TFF to
when the Output pin drives valid data
All
3.82
ns
Notes:
1.
The numbers in this table are tested using the methodology presented in Table 27 and are based on the operating conditions set forth in
2.
This time requires adjustment whenever a signal standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data
Output. When this is true, add the appropriate Output adjustment from Table 26.
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