
ADVANCE INFORMATION
33
8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER
T
RHDZ
2
T
RHLH
2
T
RHLH
1
T
WHLH
T
AVDV
1
T
AVRL
T
AVWL
1
T
AVWL
2
NOTES:
1.
2.
3.
4.
5.
Data Float After PSEN# or RD# High
T
CLK
+ 10 [max]
T
CLK
+ 10 [min]
10 [min]
1.5 T
CLK
- 5 [max]
(1.5)T
CLK
- 7 [min]
(0.5)T
CLK
- 7 [min]
(1.5)T
CLK
- 7 [min]
(1.5+M+N)T
CLK
- 28 [max]
(0.5+M)T
CLK
+ 10 [min]
(0.5+M)T
CLK
+ 10 [min]
(1+M)T
CLK
+ 10 [min]
RD# or PSEN# High to ALE High (data)
PSEN# High to ALE High (inst.)
WR# High to ALE High
T
CLK
+ 10 [min]
(2+M+N)T
CLK
- 60 [max]
(1+M)T
CLK
- 40 [min]
(1+M)T
CLK
- 40 [min]
(1+M)T
CLK
- 17 [min]
Address (mux’ed) Valid to Valid Data/Inst. In
Address Valid to RD# or PSEN# Low
Address (mux’ed) Valid to WR# Low
Address (demux’ed) Valid to WR# Low
Table 21. 8x930Ax3 and 8x930Ax4 Real-time Wait State AC Timing Specifications
Symbol (Parameter)
F
Variable
Default Data Float Timing (ns)
(EDF#=1)
F
Variable
Extended Data Float Timing (ns)
(EDF#=0)
Min
Typ
Max
Min
Typ
Max
T
(PSEN# or RD# Low to
Wait Setup)
0
0.5 T
CLK
- 13
0
0.5 T
CLK
- 35
T
WLYV
(WR# Low to Wait Setup)
0
0.5 T
CLK
- 13
0.5 T
CLK
- 35
Table 20. 8x930Ax3 and 8x930Ax4 Default and Extended Data Float Timings (Continued)
Sym-
bol
Parameter
Default Data Float
Timing (ns)
Compatibility Mode
(EDF# =1) (1,2,4,5)
Extended Data Float
Timing (ns)
Increased T
mode
(EDF#=0) (1,3,4,5)
Worst-case numbers based on silicon data collected to date.
Device configured with default data float timing for fast memory interface.
Device configured with extended data float timing for slow memory interface.
The values listed are for 12 MHz. For 6 MHz, the value of T
will double and will equal 166.6 ns.
M=0,1 is the extended ALE state; N= 0,1,2,3 is the RD#/PSEN#/WR# wait state.