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參數(shù)資料
| 型號： | X930A |
| 廠商： | Intel Corp. |
| 英文描述： | UNIVERSAL SERIAL BUS MICROCONTROLLER |
| 中文描述： | 通用串行總線的微控制器 |
| 文件頁數(shù)： | 35/38頁 |
| 文件大?。?/td> | 283K |
| 代理商： | X930A |
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ADVANCE INFORMATION
31
8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER
8.0
SPECIFICATION SUPPLEMENT
FOR 8X930AX3 AND 8X930AX4
All descriptions above apply to the 8x930Axand
8x930Ax2 microcontrollers. The following specifica-
tions apply to recent steppings of the 8x930Ax
(8x930Ax3 and 8x930Ax4). This information is in
addition to (or in place of) the specifications
described above.
8.1
Six Endpoint Pairs Functionality
In the default state, the SIXEPPEN bit of
8x930Ax
3’s and 8
x
930A
x
4’s EPCONFIG SFR is
cleared and the 6 endpoint pair feature is disabled.
In this state, the endpoint pairs of the 8
x
930A
x
3 and
8
x
930A
x
4 are similar to those of the 8
x
930A
x
and
8
x
930A
x
2 devices.
To enable the 6 endpoint pair feature, set
EPCONFIG’s SIXEPPEN bit. The 8
x
930A
x
3 and
8
x
930A
x
4 will then have the endpoint pairs shown
in Table 17.
When the 6 endpoint pair feature is enabled, two
additional SFRs — the Function Interrupt Enable
Register 1 (FIE1) and the Function Interrupt Flag
Register 1 (FIFLG1) — are enabled to manage
interrupts for the additional endpoint pairs.
See the
8x930Ax, 8x930Hx Universal Serial Bus
Microcontroller User’s Manual
for additional infor-
mation.
8.2
DC Characteristics
The V
specification given in the DC Character-
istics section of this datasheet is changed to V
=
{min} V
– 1.7 V when I
OH
= -60 μA for the A3
stepping onward.
8.3
Extended Data Float (EDF) AC
Timing Feature
To provide a direct interface capability to slower
memory without the use of tristate drivers, an
extended data float (EDF) option has been added to
the 8
x
930A
x
3 and 8
x
930A
x
4. This option is
controlled by the EDF# bit (bit 3 in the UCONFIG1
configuration byte).
If the EDF# bit is configured to 1, the 8
x
930A
x
3 and
8
x
930A
x
4 behave per the current specification
(some AC timings are different). This is known as
"Compatibility Mode". Table 19 on page 32 lists the
AC characteristics in this "Compatibility Mode" that
are different compared to the 8x930Ax and
8x930Ax2. Parameters not listed in the table remain
the same as for 8
x
930A
x
and 8
x
930A
x
2.
If the 8
x
930A
x
3 and 8
x
930A
x
4 are configured with
EDF# = 0, the device will have extended data float
timings. This mode is known as the “Increased
T
Mode.” Table 20 on page 32 and Table 21
on page 33 show the parameters that are affected
when EDF#= 0.
Configuring the device with EDF# = 0 does not
affect wait state A (all regions except 01:). Wait
state A can have 0, 1, 2, or 3 wait states. EDF#=0
affects external wait state B (region 01:). The
summary of the effect EDF# has on wait states is
listed in Table 18.
Table 17. SIx Endpoint Pair Feature
EPINDEX
FFSZ1:0
Transmit
FIFO
(bytes)
Receive
FIFO
(bytes)
0xxx x000
xx
16
16
0xxx x001
00
256
256
0xxx x010
xx
32
32
0xxx x011
xx
32
32
0xxx x100
xx
32
32
0xxx x101
xx
16
16
Table 18.
Effect of “EDF#” on Wait States
EDF#
WSB#[1:0]
Wait-state
(for page 01)
1
1
1
1
11
10
01
00
0
1
2
3
0
0
0
0
11
10
01
00
1
1
3
3
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