參數(shù)資料
型號(hào)： X930A
廠商： Intel Corp.
英文描述： UNIVERSAL SERIAL BUS MICROCONTROLLER
中文描述： 通用串行總線的微控制器
文件頁(yè)數(shù)： 13/38頁(yè)
文件大小： 283K
代理商： X930A
ADVANCE INFORMATION
9
8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER
T2EX
I
Timer 2 External Input
. In timer 2 capture mode, a falling
edge initiates a capture of the timer 2 registers. In auto-
reload mode, a falling edge causes the timer 2 registers to
be reloaded. In the up-down counter mode, this signal
determines the count direction: 1 = up, 0 = down.
P1.1
TXD
O
Transmit Serial Data
. TXD outputs the shift clock in serial
I/O mode 0 and transmits serial data in serial I/O modes 1,
2, and 3.
P3.1
V
CC
PWR
Supply Voltage
. Connect this pin to the +5V supply volt-
age.
—
V
CCP
PWR
Supply Voltage for I/O buffers
. Connect this pin to the
+5V supply voltage.
—
V
SS
V
SSP
WAIT#
GND
Circuit Ground
. Connect this pin to ground.
—
GND
Circuit Ground for I/O buffers
. Connect this pin to ground.
—
I
Real-time Wait State Input.
The real-time WAIT# input is
enabled by writing a logical ‘1’ to the WCON.0 (RTWE) bit
at S:A7H. During bus cycles, the external memory system
can signal ‘system ready’ to the microcontroller in real time
by controlling the WAIT# input signal on the port 1.6 input.
P1.6/CEX3
WCLK
O
Wait Clock Output.
The real-time WCLK output is driven at
port 1.7 (WCLK) by writing a logical ‘1’ to the WCON.1
(RTWCE) bit at S:A7H. When enabled, the WCLK output
produces a square wave signal with a period of T
CLK
.
Write
. Write signal output to external memory.
P1.7/CEX4/A17
WR#
O
P3.6
XTAL1
I
Input to the On-chip, Inverting, Oscillator Amplifier
. To
use the internal oscillator, a crystal/resonator circuit is con-
nected to this pin. If an external oscillator is used, its output
is connected to this pin. XTAL1 is the clock source for inter-
nal timing.
—
XTAL2
O
Output of the On-chip, Inverting, Oscillator Amplifier
. To
use the internal oscillator, a crystal/resonator circuit is con-
nected to this pin. If an external oscillator is used, leave
XTAL2 unconnected.
—
Table 5. Signal Descriptions (Continued)
Signal
Name
Type
Description
Alternate Function
The descriptions of A15:8/P2.7:0 and AD7:0/P0.7:0 are for the nonpage-mode chip configuration. If the
chip is configured for page-mode operation, port 0 carries the lower address bits (A7:0), and port 2 car-
ries the upper address bits (A15:8) and the data (D7:0).
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