參數(shù)資料
型號： X930A
廠商： Intel Corp.
英文描述： UNIVERSAL SERIAL BUS MICROCONTROLLER
中文描述： 通用串行總線的微控制器
文件頁數(shù)： 17/38頁
文件大?。?/td> 283K
代理商： X930A
ADVANCE INFORMATION
13
8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER
5.2
DC Characteristics
Table 9. DC Characteristics at Operating Conditions
Symbol
Parameter
Min
Typical (1)
Max
Units
Test Conditions
V
IL
Input Low Voltage
(Except EA#)
-0.5
0.2 V
CC
– 0.1
V
V
IL
1
Input Low Voltage
(EA#)
0
0.2 V
CC
– 0.3
V
V
IH
Input High Voltage
(Except XTAL1, RST)
0.2 V
CC
+ 0.9
V
CC
+ 0.5
V
V
IH
1
Input High Voltage
(XTAL1, RST)
0.7 V
CC
V
CC
+ 0.5
V
V
OL
Output Low Voltage
(Port 1, 2, 3)
0.3
0.45
1.0
V
I
OL
= 100 μA (2, 3)
I
OL
= 1.6 mA
I
OL
= 3.5 mA
I
OL
= 200 μA (2, 3)
I
OL
= 3.2 mA
I
OL
= 7.0 mA
I
OH
= -10 μA (4)
I
OH
= -30 μA
I
OH
= -60 μA
I
OH
= -200 μA (4)
I
OH
= -3.2 mA
I
OH
= -7.0 mA
V
IN
= 0.45 V
V
OL
1
Output Low Voltage
(Port 0, ALE, PSEN#,
SOF#)
0.3
0.45
1.0
V
V
OH
Output High Voltage
(Port 1, 2, 3,ALE,
PSEN#, SOF#)
V
CC
– 0.3
V
CC
– 0.7
V
CC
– 1.5
V
CC
– 0.3
V
CC
– 0.7
V
CC
– 1.5
V
V
OH
1
Output High Voltage
(Port 0 in External
Address)
V
I
IL
Logical 0 Input
Current (Port 1,2,3)
–150
μA
I
LI
Input Leakage Current
(Port 0)
±
10
μA
0.45 < V
IN
< V
CC
NOTE:
1.
2.
Typical values are obtained using V
= 5.0V, T
A
= 25°C and are not guaranteed.
Under steady state (non-transient) conditions, I
OL
must be externally limited as follows:
Maximum I
OH
per port pin:10 mA
Maximum I
per 8-bit port:
Port 0: 26 mA
Ports 1-3: 15 mA
Maximum Total I
for all output pins: 71 mA
If I
exceeds the test conditions, V
may exceed the related specification. Pins are not guaranteed
to sink current greater than the listed test conditions.
Capacitive loading on Ports 0 and 2 may cause spurious noise pulses above 0.4 V on the low-level
outputs of ALE and Ports 1, 2 and 3. The noise is due to external bus capacitance discharging into the
Port 0 and Port 2 pins when these pins change from 1 to 0. In applications where capacitive loading
exceeds 100pF, the noise pulses on these signals may exceed 0.8 V. It may be desirable to qualify
ALE or other signals with a Schmitt Trigger or CMOS-level input logic.
Capacitive loading on Ports 0 and 2 cause the V
OH
on ALE and PSEN to drop below the V
CC
specifica-
tion when the address lines are stabilizing.
The abbreviations “LS” and “FS” indicate “Low Speed” and “Full Speed,” respectively.
3.
4.
5.
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