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參數(shù)資料
| 型號(hào)： | X930A |
| 廠商： | Intel Corp. |
| 英文描述： | UNIVERSAL SERIAL BUS MICROCONTROLLER |
| 中文描述： | 通用串行總線的微控制器 |
| 文件頁數(shù)： | 19/38頁 |
| 文件大?。?/td> | 283K |
| 代理商： | X930A |
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ADVANCE INFORMATION
15
8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER
5.3
Definition of AC Symbols
I
CC
(5)
Active I
CC
60
mA
PLLSEL = 110
3 MHz – FS
(in low clock mode)
150
PLLSEL = 110
12 MHz – FS
(not in low clock
mode)
45
PLLSEL = 001
3 MHz – LS
75
PLLSEL = 100
6 MHz – LS
Table 10. AC Timing Symbol Definitions
Signals
Conditions
A
Address
H
High
D
Data In
L
Low
L
ALE
V
Valid
Q
Data Out
X
Hold
R
RD#/PSEN#
Z
Floating
W
WR#
Table 9. DC Characteristics at Operating Conditions (Continued)
Symbol
Parameter
Min
Typical (1)
Max
Units
Test Conditions
NOTE:
1.
2.
Typical values are obtained using V
= 5.0V, T
A
= 25°C and are not guaranteed.
Under steady state (non-transient) conditions, I
OL
must be externally limited as follows:
Maximum I
OH
per port pin:10 mA
Maximum I
per 8-bit port:
Port 0: 26 mA
Ports 1-3: 15 mA
Maximum Total I
for all output pins: 71 mA
If I
exceeds the test conditions, V
may exceed the related specification. Pins are not guaranteed
to sink current greater than the listed test conditions.
Capacitive loading on Ports 0 and 2 may cause spurious noise pulses above 0.4 V on the low-level
outputs of ALE and Ports 1, 2 and 3. The noise is due to external bus capacitance discharging into the
Port 0 and Port 2 pins when these pins change from 1 to 0. In applications where capacitive loading
exceeds 100pF, the noise pulses on these signals may exceed 0.8 V. It may be desirable to qualify
ALE or other signals with a Schmitt Trigger or CMOS-level input logic.
Capacitive loading on Ports 0 and 2 cause the V
OH
on ALE and PSEN to drop below the V
CC
specifica-
tion when the address lines are stabilizing.
The abbreviations “LS” and “FS” indicate “Low Speed” and “Full Speed,” respectively.
3.
4.
5.
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