參數(shù)資料
型號(hào): W989D6CBGX7E
廠(chǎng)商: WINBOND ELECTRONICS CORP
元件分類(lèi): DRAM
英文描述: 32M X 16 DDR DRAM, 5.4 ns, PBGA54
封裝: 8 X 9 MM, 0.80 MM PITCH, HALOGEN FREE AND LEAD FREE, VFBGA-54
文件頁(yè)數(shù): 8/67頁(yè)
文件大?。?/td> 1469K
代理商: W989D6CBGX7E
W989D6CB / W989D2CB
512Mb Mobile LPSDR
Publication Release Date: Jun, 27, 2011
- 16 -
Revision A01-004
Current State
CS
RAS
CAS
WE
Address
Command
Action
Notes
Read with
auto
precharge
H
X
DSL
Continue burst to end
L
H
X
NOP
Continue burst to end
L
H
L
X
BST
ILLEGAL
L
H
L
H
BS, CA, A10
READ/READA
ILLEGAL
3
L
H
L
BS, CA, A10
WRIT/WRITA
ILLEGAL
3
L
H
BS, RA
ACT
ILLEGAL
3
L
H
L
BS, A10
PRE/PREA
ILLEGAL
3
L
H
X
AREF/SELF
ILLEGAL
L
Op-Code
MRS/EMRS
ILLEGAL
Write with
auto
precharge
H
X
DSL
Continue burst to end
L
H
X
NOP
Continue burst to end
L
H
L
X
BST
ILLEGAL
L
H
L
H
BS, CA, A10
READ/READA
ILLEGAL
3
L
H
L
BS, CA, A10
WRIT/WRITA
ILLEGAL
3
L
H
BS, RA
ACT
ILLEGAL
3
L
H
L
BS, A10
PRE/PREA
ILLEGAL
3
L
H
X
AREF/SELF
ILLEGAL
L
Op-Code
MRS/EMRS
ILLEGAL
Precharging
H
X
DSL
Nop
→ Idle after tRP
L
H
X
NOP
Nop
→ Idle after tRP
L
H
L
X
BST
ILLEGAL
L
H
L
H
BS, CA, A10
READ/READA
ILLEGAL
3
L
H
L
BS, CA, A10
WRIT/WRITA
ILLEGAL
3
L
H
BS, RA
ACT
ILLEGAL
3
L
H
L
BS, A10
PRE/PREA
Nop
→ Idle after tRP
L
H
X
AREF/SELF
ILLEGAL
L
Op-Code
MRS/EMRS
ILLEGAL
Row
activating
H
X
DSL
Nop
→ Row active after tRCD
L
H
X
NOP
Nop
→ Row active after tRCD
L
H
L
X
BST
ILLEGAL
L
H
L
H
BS, CA, A10
READ/READA
ILLEGAL
3
L
H
L
BS, CA, A10
WRIT/WRITA
ILLEGAL
3
L
H
BS, RA
ACT
ILLEGAL
3
L
H
L
BS, A10
PRE/PREA
ILLEGAL
3
L
H
X
AREF/SELF
ILLEGAL
L
Op-Code
MRS/EMRS
ILLEGAL
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