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參數(shù)資料
| 型號： | W989D6CBGX7E |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | DRAM |
| 英文描述： | 32M X 16 DDR DRAM, 5.4 ns, PBGA54 |
| 封裝： | 8 X 9 MM, 0.80 MM PITCH, HALOGEN FREE AND LEAD FREE, VFBGA-54 |
| 文件頁數(shù)： | 19/67頁 |
| 文件大小： | 1469K |
| 代理商： | W989D6CBGX7E |
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W989D6CB / W989D2CB
512Mb Mobile LPSDR
Publication Release Date: Jun, 27, 2011
- 26 -
Revision A01-004
8.4 Burst Termination
The Read or Write command can be issued on any clock cycle. Whenever a Read operation is to be interrupted by a Write command,
the output data must be masked by DQM to avoid I/O conflict. Also, when a Write operation is to be interrupted by a Read command,
only the input data before the Read command is enable and the input data after the Read command is disabled.
- Read Interrupted by a Precharge
A Precharge command can be issued to terminate a Burst cycle early. When a Burst Read cycle is interrupted by a Precharge
command, the read operation is terminated after (
CAS latency-1) clock cycles from the Precharge command.
- Write Interrupted by a Precharge
A burst Write cycle can be interrupted by a Precharge command, the input circuit is reset at the same clock cycle at which the
Precharge command is issued. In this case, the DQM signal must be asserted high to prevent writing the invalid data to the cell
array.
- Read Interrupted by a Burst Stop
When the Burst Stop command is issued for the bank in a Burst cycle, the Burst operation is terminated. When the Burst Stop
command is issued during a Burst Read cycle, the read operation is terminated after clock cycle of (
CAS latency-1) from the Burst
Stop command.
- Write Interrupted by a Burst Stop
When the Burst Stop command is issued during a Burst Write cycle, the write operation is terminated at the same clock cycle that
the Burst Stop command is issued.
- Write Interrupted by a Read
A burst of write operation can be interrupted by a read command. The read command interrupts the write operation on the same
clock that the read command is issued. All the burst writes that are presented on the data bus before the read command is issued
will be written to the memory. Any remaining burst writes will be ignored once the read command is activated. There must be at
least one clock bubble (Hi-Z state) on the data bus to avoid bus contention.
- Read Interrupted by a Write
A burst of read operation can be interrupted by a write command by driving output drivers in a Hi-Z state using DQM before write to
avoid data conflict. DQM should be utilized if there is data from a Red command on the first and second cycles of the subsequent
write cycles to ensure the read data are tri-stated. From the third clock cycle, the write command will control the data bus and DQM
is not needed.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| W989D6CBGX7G | 制造商:WINBOND 制造商全稱:Winbond 功能描述:512Mb Mobile LPSDR |
| W989D6KBGX7E | 制造商:Winbond Electronics Corp 功能描述:IC LPSDR SDRAM 512MBIT 54VFBGA |
| W98AD2KBJX6E | 制造商:Winbond Electronics Corp 功能描述:IC MEMORY SDRAM 1GB 90VFBGA |
| W98AD2KBJX6I | 制造商:Winbond Electronics Corp 功能描述:IC MEMORY SDRAM 1GB 90VFBGA |
| W98M9640 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Semiconductor Discrete Device, P-Channel Power MOS Field Effect Transistor |
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