參數(shù)資料
型號: W989D6CBGX7E
廠商: WINBOND ELECTRONICS CORP
元件分類: DRAM
英文描述: 32M X 16 DDR DRAM, 5.4 ns, PBGA54
封裝: 8 X 9 MM, 0.80 MM PITCH, HALOGEN FREE AND LEAD FREE, VFBGA-54
文件頁數(shù): 24/67頁
文件大?。?/td> 1469K
代理商: W989D6CBGX7E
W989D6CB / W989D2CB
512Mb Mobile LPSDR
Publication Release Date: Jun, 27, 2011
- 30 -
Revision A01-004
8.5.7 CAS Latency field (A6~A4)
This field specifies the number of clock cycles from the assertion of the Read command to the first data read. The minimum values of
CAS Latency depends on the frequency of CLK. The minimum value which satisfies the following formula must be set in this field.
A6
A5
A4
CAS Latency
0
1
0
2 clock
0
1
3 clock
Reserved bits (A7, A8, A10, A11, A12, BA0, BA1)
These bits are reserved for future operations. They must be set to 0 for normal operation.
Single Write mode (A9)
This bit is used to select the write mode. When the A9 bit is 0, Burst Read and Burst Write mode are selected. When the A9 bit is
1, Burst Read and Single Write mode are selected.
A9
Write Mode
0
Burst Read and Burst Write
1
Burst Read and Single Write
8.5.8 Mode Register Definition
A0
A3
A0
Addressing Mode
A0
0
A0
Sequential
A0
1
A0
Interleave
A0
A9
Single Write Mode
A0
0
A0
Burst read and Burst write
A0
1
A0
Burst read and single write
A0
A2
A1
A0
0
A0
0
1
A0
0
1
0
A0
0
1
A0
1
0
A0
1
0
1
A0
1
0
A0
1
A0
Burst Length
A0
Sequential
A0
Interleave
1
A0
1
A0
2
A0
2
A0
4
A0
4
A0
8
A0
8
A0
Reserved
A0
Reserved
A0
Full Page
A0
CAS Latency
A0
Reserved
2
A0
3
Reserved
A0
A6
A5
A4
A0
0
A0
0
1
0
A0
0
1
A0
1
0
A0
0
1
A0
A1
A2
A3
A4
A5
A6
Burst Length
Addressing Mode
CAS Latency
A8
Reserved
A0
A7
A0
A9
A0
Write Mode
A10
A0
A11
BA0
"0"
A0
Reserved
"0"
BA1
"0"
A12
Reserved
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