- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄68560 > W989D6CBGX7E (WINBOND ELECTRONICS CORP) 32M X 16 DDR DRAM, 5.4 ns, PBGA54 PDF資料下載
參數(shù)資料
| 型號： | W989D6CBGX7E |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | DRAM |
| 英文描述： | 32M X 16 DDR DRAM, 5.4 ns, PBGA54 |
| 封裝： | 8 X 9 MM, 0.80 MM PITCH, HALOGEN FREE AND LEAD FREE, VFBGA-54 |
| 文件頁數(shù)： | 45/67頁 |
| 文件大?。?/td> | 1469K |
| 代理商： | W989D6CBGX7E |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁當前第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁
W989D6CB / W989D2CB
512Mb Mobile LPSDR
Publication Release Date: Jun, 27, 2011
- 5 -
Revision A01-004
4. PIN DESCRIPTION
4.1 Signal Description
BALL NAME
FUNCTION
DESCRIPTION
A [n : 0]
Address
Multiplexed pins for row and column address.
A10 is Auto Precharge Select
BA0, BA1
Bank Select
Select bank to activate during row address latch time, or bank to
read/write during address latch time.
DQ0~DQ15 (×16)
DQ0~DQ31 (×32)
Data Input/ Output Multiplexed pins for data output and input.
CS
Chip Select
Disable or enable the command decoder. When command
decoder is disabled, new command is ignored and previous
operation continues.
RAS
Row
Address Strobe
Command input. When sampled at the rising edge of the clock,
RAS , CAS and
WE define the operation to be executed.
CAS
Column
Address Strobe
Referred to RAS
WE
Write Enable
Referred to
WE
UDQM / LDQM(x16)
DQM0 ~ DQM3 (x32)
I/O Mask
The output buffer is placed at Hi-Z (with latency of 2 in CL=2, 3;)
when DQM is sampled high in read cycle. In write cycle, sampling
DQM high will block the write operation with zero latency.
CLK
Clock Inputs
System clock used to sample inputs on the rising edge of clock.
CKE
Clock Enable
CKE controls the clock activation and deactivation. When CKE is
low, Power Down mode, Suspend mode or Self Refresh mode is
entered.
VDD
Power
Power supply for input buffers and logic circuit inside DRAM.
VSS
Ground
Ground for input buffers and logic circuit inside DRAM.
VDDQ
Power for I/O
Buffer
Power supply separated from VDD, used for output buffers to
improve noise.
VSSQ
Ground for
I/O Buffer
Separated ground from VSS, used for output buffers to improve
noise.
NC
No Connection
No connection
4.2 Addressing Table
ITEM
512 Mb
Number of banks
4
Bank address pins
BA0,BA1
Auto precharge pin
A10/AP
X16
Row addresses
A0-A12
Column addresses
A0-A9
Refresh count
8K
x32
Row addresses
A0-A12
Column addresses
A0-A8
Refresh count
8K
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| W99802G | SPECIALTY TELECOM CIRCUIT, PBGA184 |
| WAC-011-A | TRANSCEIVER, PQFP100 |
| WAC-011-A | TRANSCEIVER, PQFP100 |
| WAC-021-C | ATM SEGMENTATION AND REASSEMBLY DEVICE, PQFP240 |
| WAC-021-C | ATM SEGMENTATION AND REASSEMBLY DEVICE, PQFP240 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W989D6CBGX7G | 制造商:WINBOND 制造商全稱:Winbond 功能描述:512Mb Mobile LPSDR |
| W989D6KBGX7E | 制造商:Winbond Electronics Corp 功能描述:IC LPSDR SDRAM 512MBIT 54VFBGA |
| W98AD2KBJX6E | 制造商:Winbond Electronics Corp 功能描述:IC MEMORY SDRAM 1GB 90VFBGA |
| W98AD2KBJX6I | 制造商:Winbond Electronics Corp 功能描述:IC MEMORY SDRAM 1GB 90VFBGA |
| W98M9640 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Semiconductor Discrete Device, P-Channel Power MOS Field Effect Transistor |
發(fā)布緊急采購，3分鐘左右您將得到回復。