參數(shù)資料
型號(hào): W989D6CBGX7E
廠商: WINBOND ELECTRONICS CORP
元件分類: DRAM
英文描述: 32M X 16 DDR DRAM, 5.4 ns, PBGA54
封裝: 8 X 9 MM, 0.80 MM PITCH, HALOGEN FREE AND LEAD FREE, VFBGA-54
文件頁(yè)數(shù): 3/67頁(yè)
文件大?。?/td> 1469K
代理商: W989D6CBGX7E
W989D6CB / W989D2CB
512Mb Mobile LPSDR
Publication Release Date: Jun, 27, 2011
- 11 -
Revision A01-004
6.6 AC Characteristics And AC Operating Conditions
6.6.1 AC Characteristics
*CL= CAS Latency; (Notes: 5,6,7)
PARAMETER
SYM
-6
-75
UNIT
NOTE
MIN.
MAX.
MIN.
MAX.
Ref/Active to Ref/Active
Command Period
tRC
60
72.5
-
ns
8
Active to precharge
Command Period
tRAS
42
100000
50
100000
ns
8
Active to Read/Write
Command Delay Time
tRCD
18
-
ns
8
Read/Write(a) to
Read/Write(b)Command
Period
tCCD
1
-
CLK
8
Precharge to Active
Command Period
tRP
18
-
ns
8
Active(a) to Active(b)
Command Period
tRRD
12
15
-
ns
8
Write Recovery Time
tWR
15
-
ns
Write-Recovery Time
(Last data to Read)
tLDR
1
CLK
CLK Cycle Time
CL * = 3
tCK
6
1000
7.5
1000
ns
CL * = 2
12
1000
12
1000
ns
CLK High Level width
tCH
2
2.5
-
ns
CLK Low Level width
tCL
2
2.5
-
ns
Access Time from CLK
CL * = 3
tAC
5.4
-
5.4
ns
CL * = 2
6
-
8
ns
Output Data Hold Time
tOH
2.5
-
ns
Output Data High
Impedance Time
CL * = 3
tHZ
5.4
-
5.4
ns
7
CL * = 2
6
-
6
ns
7
Output Data Low
Impedance Time
tLZ
1
-
ns
Power Down Mode
Entry Time
tSB
0
6
0
7.5
ns
Transition Time of CLK
(Rise and Fall)
tT
0.3
1.2
0.3
1.2
ns
Data-in Set-up Time
tDS
1.5
-
ns
Data-in Hold Time
tDH
1
-
ns
Address Set-up Time
tAS
1.5
-
ns
Address Hold Time
tAH
1
-
ns
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