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參數(shù)資料
| 型號： | W981204AH-8H |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | DRAM |
| 英文描述： | 32M X 4 SYNCHRONOUS DRAM, 6 ns, PDSO54 |
| 封裝： | 0.400 INCH, 0.80 MM PITCH, TSOP2-54 |
| 文件頁數(shù)： | 4/42頁 |
| 文件大?。?/td> | 1082K |
| 代理商： | W981204AH-8H |
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W981204AH
8M x 4 Banks x 4 bits SDRAM
Revision 1.0
Publication Release Date: June, 2000
- 12 -
Table 2 Address Sequence of Sequential Mode
DATA
Access Address
Burst Length
Data 0
n
BL= 2 (disturb address is A0)
Data 1
n + 1
No address carry from A0 to A1
Data 2
n + 2
BL= 4 (disturb addresses are A0 and A1)
Data 3
n + 3
No address carry from A1 to A2
Data 4
n + 4
Data 5
n + 5
BL= 8 (disturb addresses are A0, A1 and A2)
Data 6
n + 6
No address carry from A2 to A3
Data 7
n + 7
. Addressing Sequence of Sequential Mode
A column access is performed by increasing the address from the column address which is input to the
device. The disturb address is varied by the Burst Length as shown in Table 2.
. Addressing Sequence of Interleave Mode
A column access is started in the input column address and is performed by inverting the address bit in the
sequence shown in Table 3.
Table 3 Address Sequence of Interleave Mode
DATA
Access
Address
Burst Length
Data 0
A8 A7 A6 A5 A4 A3 A2 A1 A0
BL = 2
Data 1
A8 A7 A6 A5 A4 A3 A2 A1 A0
Data 2
A8 A7 A6 A5 A4 A3 A2 A1 A0
BL = 4
Data 3
A8 A7 A6 A5 A4 A3 A2 A1 A0
Data 4
A8 A7 A6 A5 A4 A3 A2 A1 A0
Data 5
A8 A7 A6 A5 A4 A3 A2 A1 A0
BL = 8
Data 6
A8 A7 A6 A5 A4 A3 A2 A1 A0
Data 7
A8 A7 A6 A5 A4 A3 A2 A1 A0
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W981208AH | 制造商:WINBOND 制造商全稱:Winbond 功能描述:4M x 8 bit x 4 Banks SDRAM |
| W981208AH-75 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:x8 SDRAM |
| W981208AH-8H | 制造商:WINBOND 制造商全稱:Winbond 功能描述:x8 SDRAM |
| W981208BH | 制造商:WINBOND 制造商全稱:Winbond 功能描述:4M x 4 BANKS x 8 BIT SDRAM |
| W981208BH-7 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:x8 SDRAM |
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