參數(shù)資料
型號: W981204AH-8H
廠商: WINBOND ELECTRONICS CORP
元件分類: DRAM
英文描述: 32M X 4 SYNCHRONOUS DRAM, 6 ns, PDSO54
封裝: 0.400 INCH, 0.80 MM PITCH, TSOP2-54
文件頁數(shù): 39/42頁
文件大?。?/td> 1082K
代理商: W981204AH-8H
W981204AH
8M x 4 Banks x 4 bits SDRAM
Revision 1.0
Publication Release Date: June, 2000
- 6 -
AC CHARACTERISTICS AND OPERATING CONDITION
(Vcc=3.3V
±0.3V, Ta=0° to 70°C Notes: 5, 6, 7, 8)
-75 (PC133)
-8H (PC100)
SYMBOL
PARAMETER
MIN
MAX
MIN
MAX
UNIT
tRC
Ref/Active to Ref/Active Command Period
65
68
tRAS
Active to precharge Command Period
45
100000
48
100000
ns
tRCD
Active to Read/Write Command Delay Time
20
tCCD
Read/Write(a) to Read/Write(b)Command Period
1
cycle
tRP
Precharge to Active Command Period
20
tRRD
Active(a) to Active(b) Command Period
15
20
tWR
Write Recovery Time
CL*=2
10
CL*=3
7.5
8
tCK
CLK Cycle Time
CL*=2
10
1000
10
1000
CL*=3
7.5
1000
8
1000
tCH
CLK High Level width
2.5
3
tCL
CLK Low Level width
2.5
3
tAC
Access Time from CLK
CL*=2
6
CL*=3
5.4
6
ns
tOH
Output Data Hold Time
2.7
3
tHZ
Output Data High Impedance Time
2.7
7.5
3
8
tLZ
Output Data Low Impedance Time
0
tSB
Power Down Mode Entry Time
0
7.5
0
8
tT
Transition Time of CLK (Rise and Fall)
0.5
10
0.5
10
tDS
Data-in Set-up Time
1.5
2
tDH
Data-in Hold Time
0.8
1
tAS
Address Set-up Time
1.5
2
tAH
Address Hold Time
0.8
1
tCKS
CKE Set-up Time
1.5
2
tCKH
CKE Hold Time
0.8
1
tCMS
Command Set-up Time
1.5
2
tCMH
Command Hold Time
0.8
1
tREF
Refresh Time
64
ms
tRSC
Mode register Set Cycle Time
15
16
ns
*CL=CAS Latency
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