<button id="a3t5b"></button>
        



    






  

    
    
    
  

  
  











 
 




 
 




    



參數(shù)資料









型號(hào)：
W9412G2IB-4




廠商：
WINBOND ELECTRONICS CORP




元件分類：
DRAM




英文描述：
4M X 32 DDR DRAM, 0.6 ns, PBGA144




封裝：
12 X 12 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, LFBGA-144




文件頁(yè)數(shù)：
48/50頁(yè)




文件大小：
826K




代理商：
W9412G2IB-4








	

    
    

    

	
W9412G2IB
Publication Release Date: Aug. 30, 2010
- 7 -
Revision A06
5. BALL DESCRIPTION
BALL LOCATION PIN NAME
FUNCTION
DESCRIPTION
M4-M10, L5-L8, K5
A0
A11
Address
Multiplexed pins for row and column address.
Row
address: A0
A11. Column address: A0A7. (A8 is used
for Auto-precharge)
M3, L4
BA0, BA1
Bank Address
Select bank to activate during row address latch time, or
bank to read/write during column address latch time.
A4-A9,B1,B5,B8,
B12,C1,C2,C11,C1
2,D1,D12,E1,E2,E1
1,E12,F1,F2,F11,F1
2,H1,H2,H11,H12,J
1,J2,J11,J12
DQ0
DQ31 Data Input/ Output The DQ0DQ31 input and output data are synchronized
with both edges of DQS.
A1,A12,G1,G12
DQS0
DQS3
Data Strobe
DQS is Bi-directional signal. DQS is input signal during
write operation and output signal during read operation.
It is Edge-aligned with read data, Center-aligned with
write data.
M1
CS
Chip Select
Disable or enable the command decoder. When
command decoder is disabled, new command is ignored
and previous operation continues.
K1,K2,L1
RAS , CAS ,
WE
Command Inputs Command inputs (along with CS ) define the command
being entered.
A2,A11,G2,G11
DM0
DM3
Write mask
DM is an input mask signal for writes data. When DM is
asserted “high” in burst write, the input data is masked.
DM is synchronized with both edges of DQS.
L10,L11
CLK,
CLK
Differential clock
inputs
All address and control input signals are sampled on the
crossing of the positive edge of CLK and negative edge
of CLK .
M11
CKE
Clock Enable
CKE controls the clock activation and deactivation. CKE
is synchronous for POWER-DOWN entry and exit, and
for SELF REFRESH entry CKE must be maintained high
throughout READ and WRITE accesses. Input buffers,
excluding CLK, CLK and CKE are disabled during
POWER-DOWN. Input buffers, excluding CKE are
disabled during SELF REFRESH.
M12
VREF
Reference Voltage VREF is reference voltage for inputs.
C6,C7,D3,D10,K3,K
6, K7,K10
VDD
Power ( +2.5V )
Power for logic circuit inside DDR SDRAM.

    

    
    








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參數(shù)描述






W9412G2IB-5
 制造商:Winbond Electronics Corp 功能描述:8*16 DDR1




W9412G6CH
 制造商:WINBOND 制造商全稱:Winbond 功能描述:2M 】 4 BANKS 】 16 BITS DDR SDRAM




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 制造商:WINBOND 制造商全稱:Winbond 功能描述:2M × 4 BANKS × 16 BITS DDR SDRAM




W9412G6IH-5
功能描述:IC DDR-400 SDRAM 128MB 66TSSOPII RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲(chǔ)器:EEPROMs - 串行 存儲(chǔ)器類型:EEPROM 存儲(chǔ)容量:4K (512 x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:2.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:8-MFP 包裝:帶卷 (TR)




W9412G6JH
 制造商:WINBOND 制造商全稱:Winbond 功能描述:2M ? 4 BANKS ? 16 BITS DDR SDRAM




    
    
    
	
	
    
    
     
     
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