參數(shù)資料
型號(hào)： W78E354P
廠商： WINBOND ELECTRONICS CORP
元件分類： 微控制器/微處理器
英文描述： MONITOR MICROCONTROLLER
中文描述： 8-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQCC68
封裝： PLASTIC, LCC-68
文件頁(yè)數(shù)： 33/45頁(yè)
文件大?。?/td> 430K
代理商： W78E354P
W78E354
Publication Release Date: April 1997
- 33 -
Revision A1
V
PP
is the high voltage input while in Flash Mode.
A<0:14>
is the address bus of the Flash cell while
in Flash Mode.
Dout<0:7>
is the data bus output of the Flash cell and
Din<0:7>
is the data bus input
while the chip is in Flash mode. The
A9CTRL, A13CTRL,
A14CTRL
and
OECTRL
signals are used
to select the Flash Mode. The
OE
and
CE
signals are the control strobe signals for Flash Mode
operation. These signals are operational only in Flash Mode and appear as inputs/outputs via the
external pins with a "Test Name" as listed in the Pin Description in Sec. D.
During normal operation, the critical timing parameter is the Flash data access time. When operating
at 24 MHz, the Flash cell requires 150 nS after an address out until the data is valid, as shown below.
Timing for Flash ROM Data Access
0000
0001
0002
ROM
Address
A<0:14>
ROM
Data
Dout<0:7>
#AAH
Sample
Clock
Max. 150 nS for 24 MHz
B. Option Setting Bits
The
Option setting bits
are used to set user-selectable options. These bits are programmed in the
same way as the 16K byte Flash ROM except for the address A<14:0> which is 7FFFH.
MSB
LSB
B4
B3
B2
B1
Note: Default value is 1 for each bit.
B1: EnWDT_Bit. (1: Disable, 0:Enable)
This bit is used to enable/disable the Watchdog Timer operation.
(B3, B2): WatchDog Timer period set.
These two bits are used to set the time period of the Watchdog timer.
(0, 0): 219/fosc sec.
(0, 1): 221/fosc sec.
(1, 0): 223/fosc sec.
(1, 1): 224/fosc sec.
Where fosc is the crystal frequency.
B4: EnSVS_Bit. (1: Disable, 0:Enable)
This bit is used to enable/disable the Power-low-detection function.
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