參數(shù)資料
型號: W78E354P
廠商: WINBOND ELECTRONICS CORP
元件分類: 微控制器/微處理器
英文描述: MONITOR MICROCONTROLLER
中文描述: 8-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQCC68
封裝: PLASTIC, LCC-68
文件頁數(shù): 27/45頁
文件大?。?/td> 430K
代理商: W78E354P
W78E354
Publication Release Date: April 1997
- 27 -
Revision A1
L. Sync Processor
Sync Processor Block Diagram
H
V
Digital
Filter
ENVS
AD[7:0]
H-Clamp
Generator
SOA
Generator
VSPS
HSPS
DUMMYEN
1
0
0
0
0
0
1
1
1
1
VDISHC
H/V Dummy
Sync
Generator
HDUMMY
VDUMMY
VSEP
VREST
HREST
H
SOA
H-Clamp
V
H/V
Frequency
Counter
Vsync
Separator
Polarity
Detect &
Restoration
IN
IN
OUT
OUT
a. H/V Sync Digital Filter
Both Hsync and Vsync inputs have an internal digital filter to improve noise immunity. Any pulse that
is shorter than an internal clock period will be regarded as a glitch and will be ignored.
Ex: Tclock = 62 nS @16 MHz, any sync with pulse width less than 62 nS will be regarded as a glitch.
b. Polarity Detector
The H/V polarity is detected automatically and can be read from the STATUS register, the H/V input
signals are then polarity restored (become HREST/VREST) for internal processing and output to
H
OUT
/V
OUT
to drive the deflection circuit.
The maximun sync width to H
IN
pin is: (1/Fclock )
×
16384
The maximun sync width to V
IN
pin is: (1/Fclock )
×
16384
F
CLOCK
16 MHz
18.432 MHz
20 MHz
24 MHz
Max. sync width for H
IN
1024
μ
S
1024
μ
S
888
μ
S
888
μ
S
819
μ
S
819
μ
S
681
μ
S
681
μ
S
Max. sync width for V
IN
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