
W78E354
- 22 -
16 MHz
18.432 MHz
20 MHz
24 MHz
DSCL Low
750 nS
651 nS
600 nS
499 nS
F. I
2
C Port: Serial Port 2
(S/W emulation).
G. Interrupts
The W78E354 has 6 interrupt sources. Five of them, with the exception of
INT1
(at vector address
0013H) are identical to those of the 8051 series. The remaining one (at vector address 002BH) is a
new addition. All the interrupt sources and the corresponding interrupt vector addresses for the
W78E354 are given in the following table:
SOURCE
VECTOR
DDRESS
DESCRIPTION
PRIORITY WITHIN A LEVEL
1
IE0
0003H
Same as the 8051.
Highest
2
TF0
000BH
Same as the 8051.
3
*1
0013H
Replaces
INT1
of the 8051.
4
TF1
001BH
Same as the 8051.
5
RI+TI
0023H
Same as the 8051.
6
*2
002BH
New addition.
(like TF2 + EXF2 in the 8052)
Lowest
Notes:
*1 = DSCLINT + ADCINT + TIMEOUT + SOAINT + VEVENT + PARAINT + DDC1INT.
*2 is the interrupt generated by the I2C in the DDC port.
The interrupt at vector address 0013H is driven by another seven different sources. These are 1) a
High-to-low transition of the DSCL-pin, 2) the A/D converter, 3) the Auto-reload Timer, 4) the SOA
output, 5) Vsync, 6) the Parabola interrupt generator, and 7) DDC1 in the DDC port. The programmer
must read the INTVECT register to identify the interrupt request source. These seven sources can be
masked individually by setting the corresponding bit within the INTMSK register (Bit0..6). The newly
added interrupt at vector address 002BH is driven by the I2C circuit in the DDC port.
The interrupt enable control bits for the two interrupts at 0013H and 002BH are the bits IE.2 and IE.5
in the IE register, respectively. They can be disabled by clearing IE.7 (disable all interrupts). The
interrupt priority control bits are IP.2 and IP.5 in the IP register, respectively.
The following diagram illustrates the above description.