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參數資料
| 型號： | W78E354P |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MONITOR MICROCONTROLLER |
| 中文描述： | 8-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數： | 31/45頁 |
| 文件大?。?/td> | 430K |
| 代理商： | W78E354P |
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W78E354
Publication Release Date: April 1997
- 31 -
Revision A1
Purpose:
To protect the HOT (Horizontal Oscillating Transistor) and other critical circuitry by making a quick
response when the Hsync frequency drops below the preset boundary frequency.
Operation:
When the Hsync frequency is lower than the boundary frequency for three consecutive cycles or
stopped for a certain period, the SOA pin (P1.5) will change to a "high" state (for the extenal
protection circuit to function). Writing any value to the SOACLR register will release the SOA pin.
To set the boundary frequency, one can write some formula:value to the SOAREG register according
to the SOAREG value = 2M
÷
boundary frequency
Ex: If 50 KHz is considered the boundary frequency, then SOAREG = 2M
÷
50K = 40.
No Hsync response time = 2048
×
(1/F
clock
).
16 MHz
18.432 MHz
20 MHz
24 MHz
No H response time
128
μ
S
110
μ
S
102
μ
S
85
μ
S
M. Power Supervisor, Watchdog Timer and Reset Circuitry
The reset signals come from the following three sources:
1. External reset input (active low)
2. Power low detect
3. Hardware Watchdog Timer
The power-low detection circuit generates a reset signal once the V
CC
voltage falls below 3.8V. This
reset signal is released a short time after V
CC
has increased above 4.3V. This function can be
enabled or disabled by a code option.
The purpose of a watchdog timer is to reset the CPU if it enters erroneous processor states (possibly
caused by electrical noise or RFI) within a reasonable period of time. The watchdog timer clock
source comes from the internal system clock and can be enabled or disabled by a code option. When
enabled, the watchdog circuitry will generate a system reset if the user program fails to reload the
watchdog timer (by writing any value to the WDTCLR register) within a specified length of time known
as the "watchdog interval". The watchdog interval has four code options: 219/fosc, 221/fosc, 223/fosc
and 224/fosc sec.
The block diagram of the reset circuitry is shown as follows:
Watchdog
Timer
Power-low
Detect Circuit
EnWDT_Bit
EnSVS_Bit
EN
EN
External Reset
CPU
POR
Reset the other
function blocks
XRESET
Reset all DACs
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| W78E51B | 8-BIT MTP Monitor Microcontroller(多次可編程的8位的監(jiān)視微控制器) |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| W78E365 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-bit microcontroller |
| W78E365_07 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:8-BIT MICROCONTROLLER |
| W78E365-24 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| W78E365-40 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| W78E365A | 制造商:WINBOND 制造商全稱:Winbond 功能描述:8-BIT MICROCONTROLLER |
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