參數(shù)資料
型號: W3H64M72E-667SBCF
廠商: WHITE ELECTRONIC DESIGNS CORP
元件分類: DRAM
英文描述: 64M X 72 DDR DRAM, PBGA208
封裝: 16 X 22 MM, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-208
文件頁數(shù): 20/32頁
文件大?。?/td> 944K
代理商: W3H64M72E-667SBCF
W3H64M72E-XSBX
W3H64M72E-XSBXF
27
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
December 2009
2010 White Electronic Designs Corp. All rights reserved
Rev. 9
White Electronic Designs Corp. reserves the right to change products or specications without notice.
AC TIMING PARAMETERS
(continued)
-55°C ≤ TA < +125°C
Parameter
Symbol
667Mbs CL6
533Mbs CL5
400Mbs CL4
Unit
Min
Max
Min
Max
Min
Max
Command
and
Address
Address and control input pulse
width for each input
t
IPW
0.6
tCK
Address and control input setup
time
t
ISa
400
500
600
ps
t
ISb
200
250
350
ps
Address and control input hold time
t
IHa
400
500
600
ps
t
IHb
275
375
475
ps
CAS# to CAS# command delay
t
CCD
2
tCK
ACTIVE to ACTIVE (same bank)
command
t
RC
55
ns
ACTIVE bank a to ACTIVE bank b
command
t
RRD
10
ns
ACTIVE to READ or WRITE delay
t
RCD
15
ns
Four Bank Activate period
t
FAW
505050
ns
ACTIVE to PRECHARGE
command
t
RAS
40
70,000
40
70,000
40
70,000
ns
Internal READ to precharge
command delay
t
RTP
7.5
ns
Write recovery time
t
WR
15
ns
Auto precharge write recovery +
precharge time
t
DAL
tWR + tRP
ns
Internal WRITE to READ command
delay
t
WTR
7.5
10
ns
PRECHARGE command period
t
RP
15
ns
PRECHARGE ALL command
period
t
RPA
tRP + tCK
ns
LOAD MODE command cycle time
t
MRD
2
tCK
Refresh
CKE low to CK, CK# uncertainty
t
DELAY
tIS +tIH + tCK
ns
REFRESH to Active or Refresh to
Refresh command interval
t
RFC
197.5
70,000
197.5
70,000
197.5
70,000
ns
Average periodic refresh interval
(commercial and industrial)
t
REFI
7.8
μs
Average periodic refresh interval
(military)
t
REFIM
1.95
μs
Exit self refresh to non-READ
command
t
XSNR
tRFC(MIN) + 10
ns
Exit self refresh to READ
t
XSRD
200
tCK
Exit self refresh timing reference
t
lSXR
tIS
ps
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