參數資料
型號: W3H64M72E-667SBCF
廠商: WHITE ELECTRONIC DESIGNS CORP
元件分類: DRAM
英文描述: 64M X 72 DDR DRAM, PBGA208
封裝: 16 X 22 MM, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-208
文件頁數: 1/32頁
文件大?。?/td> 944K
代理商: W3H64M72E-667SBCF
White Electronic Designs
White Electronic Designs Corp. reserves the right to change products or specications without notice.
W3H64M72E-XSBX
W3H64M72E-XSBXF
1
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
December 2009
2010 White Electronic Designs Corp. All rights reserved
Rev. 9
64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package
FEATURES
Data rate = 667, 533, 400 Mb/s
Package:
208 Plastic Ball Grid Array (PBGA), 16 x 22mm
1.0mm pitch
Single Supply Voltage = 1.8V
Differential data strobe (DQS, DQS#) per byte
Internal, pipelined, double data rate architecture
4-bit prefetch architecture
DLL for alignment of DQ and DQS transitions with
clock signal
Eight internal banks for concurrent operation
(Per DDR2 SDRAM Die)
Programmable Burst lengths: 4 or 8
Auto Refresh and Self Refresh Modes
On Die Termination (ODT)
Adjustable data – output drive strength
Programmable CAS latency: 3, 4 or 5
Posted CAS additive latency: 0, 1, 2, 3 or 4
Write latency = Read latency - 1* tCK
Commercial, Industrial and Military Temperature
Ranges
Organized as 64M x 72
Weight: W3H64M72E-XSBX - 2.5 grams typical
BENEFITS
30% Space saving vs. FBGA
Reduced part count
50% I/O reduction vs FBGA
Reduced trace lengths for lower parasitic
capacitance
Suitable for hi-reliability applications
Upgradable to 128M x 72 density (contact factory
for information)
Lead free - available (Pb free - component and
material are lead free in accordance with IPC-1752)
* This product is subject to change without notice.
Area
5 x 100mm2 = 500mm2
352mm2
30%
5 x 84 balls = 420 balls
208 Balls
50%
S
A
V
I
N
G
S
I/O
Count
W3H64M72E-XSBX
CSP Approach (mm)
84
FBGA
12.5
8
22
16
84
FBGA
12.5
84
FBGA
12.5
84
FBGA
12.5
84
FBGA
12.5
FIGURE 1 – DENSITY COMPARISONS
White Electronic Designs
W3H64M72E-XSBX
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