參數(shù)資料
型號(hào)： W3H32M72E-400SB2M
廠商： MICROSEMI CORP-PMG MICROELECTRONICS
元件分類： DRAM
英文描述： 32M X 72 DDR DRAM, 0.6 ns, PBGA208
封裝： 16 X 20 MM, 1 MM PITCH, PLASTIC, BGA-208
文件頁(yè)數(shù)： 8/25頁(yè)
文件大?。?/td> 1062K
代理商： W3H32M72E-400SB2M
W3H32M72E-XSB2X
November 2010 2010 Microsemi Corporation. All rights reserved.
16
Microsemi Corporation (602) 437-1520 www.whiteedc.com
Rev. 3
www.microsemi.com
Microsemi Corporation reserves the right to change products or specications without notice.
to any READ or WRITE commands being issued to that bank. A
PRECHARGE command is allowed if there is no open row in that
bank (idle state) or if the previously open row is already in the
process of precharging. However, the precharge period will be
determined by the last PRECHARGE command issued to the bank.
PRECHARGE OPERATION
InputA10 determines whether one or all banks are to be precharged,
and in the case where only one bank is to be precharged, inputs
BA1–BA0 select the bank. Otherwise BA1–BA0 are treated as
“Don’t Care.”
When all banks are to be precharged, inputs BA1–BA0 are treated
as “Don’t Care.” Once a bank has been precharged, it is in the
idle state and must be activated prior to any READ or WRITE
commands being issued to that bank. tRPA timing applies when the
PRECHARGE (ALL) command is issued, regardless of the number
of banks already open or closed. If a single-bank PRECHARGE
command is issued, tRP timing applies.
SELF REFRESH COMMAND
The SELF REFRESH command can be used to retain data in the
DDR2 SDRAM, even if the rest of the system is powered down.
When in the self refresh mode, the DDR2 SDRAM retains data
without external clocking. All power supply inputs (including VREF)
must be maintained at valid levels upon entry/exit and during SELF
REFRESH operation.
The SELF REFRESH command is initiated like a REFRESH
command except CKE is LOW. The DLL is automatically disabled
upon entering self refresh and is automatically enabled upon exiting
self refresh (200 clock cycles must then occur before a READ
command can be issued). The differential clock should remain
stable and meet tCKE specications at least 1 x tCK after entering
self refresh mode. All command and address input signals except
CKE are “Don’t Care” during self refresh.
The procedure for exiting self refresh requires a sequence of
commands. First, the differential clock must be stable and meet
tCK specications at least 1 x tCK prior to CKE going back HIGH.
Once CKE is HIGH (tCLE(MIN) has been satised with four clock
registrations), the DDR2 SDRAM must have NOP or DESELECT
commands issued for tXSNR because time is required for the
completion of any internal refresh in progress. A simple algorithm
for meeting both refresh and DLL requirements is to apply NOP
or DESELECT commands for 200 clock cycles before applying
any other command.
Note: Self refresh not available at military temperature..
TABLE 4 – WRITE USING CONCURRENT AUTO PRECHARGE
From Command (Bank n)
To Command (Bank m)
Minimum Delay (With Concurrent
Auto Precharge)
Units
WRITE with Auto Precharge
READ OR READ w/AP
(CL-1) + (BL/2) + tWTR
t
CK
WRITE or WRITE w/AP
(BL/2)
t
CK
PRECHARGE or ACTIVE
1
t
CK
CS#
WE#
CAS#
RAS#
CKE
A10
Bank Addresses
HIGH
ALL BANKS
ONE BANK
BA
ADDRESS
CK
CK#
DON’T CARE
FIGURE 13 – PRECHARGE COMMAND
Note: BA = bank address (if A10 is LOW; otherwise "Don't Care").
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
W3H32M72E-400SBC 制造商:Microsemi Corporation 功能描述:32M X 72 DDR2, 1.8V, 400MHZ, 208PBGA COMMERICAL TEMP. - Bulk
W3H32M72E-400SBI 制造商:Microsemi Corporation 功能描述:32M X 72 DDR2, 1.8V, 400MHZ, 208PBGA INDUSTRIAL TEMP. - Bulk
W3H32M72E-400SBM 制造商:Microsemi Corporation 功能描述:32M X 72 DDR2, 1.8V, 400MHZ, 208PBGA MIL-TEMP. - Bulk
W3H32M72E-533ES 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:32M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package
W3H32M72E-533ESC 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:32M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package
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