參數(shù)資料
型號(hào)： W3H32M72E-400SB2M
廠商： MICROSEMI CORP-PMG MICROELECTRONICS
元件分類： DRAM
英文描述： 32M X 72 DDR DRAM, 0.6 ns, PBGA208
封裝： 16 X 20 MM, 1 MM PITCH, PLASTIC, BGA-208
文件頁(yè)數(shù)： 3/25頁(yè)
文件大?。?/td> 1062K
代理商： W3H32M72E-400SB2M
W3H32M72E-XSB2X
November 2010 2010 Microsemi Corporation. All rights reserved.
11
Microsemi Corporation (602) 437-1520 www.whiteedc.com
Rev. 3
www.microsemi.com
Microsemi Corporation reserves the right to change products or specications without notice.
The EMR must be loaded when all banks are idle and no bursts
are in progress, and the controller must wait the specied time tMRD
before initiating any subsequent operation. Violating either of these
requirements could result in unspecied operation.
DLL ENABLE/DISABLE
The DLL may be enabled or disabled by programming bit E0
during the LM command, as shown in Figure 7. The DLL must
be enabled for normal operation. DLL enable is required during
power-up initialization and upon returning to normal operation after
having disabled the DLL for the purpose of debugging or evaluation.
Enabling the DLL should always be followed by resetting the DLL
using an LM command.
The DLL is automatically disabled when entering SELF REFRESH
operation and is automatically re-enabled and reset upon exit of
SELF REFRESH operation.
Any time the DLL is enabled (and subsequently reset), 200 clock
cycles must occur before a READ command can be issued, to
allow time for the internal clock to synchronize with the external
clock. Failing to wait for synchronization to occur may result in a
violation of the tAC or tDQSCK parameters.
OUTPUT DRIVE STRENGTH
The output drive strength is dened by bit E1, as shown in Figure
7. The normal drive strength for all outputs are specied to be
SSTL_18. Programming bit E1 = 0 selects normal (full strength)
drive strength for all outputs. Selecting a reduced drive strength
option (E1 = 1) will reduce all outputs to approximately 60 percent of
the SSTL_18 drive strength. This option is intended for the support
of lighter load and/or point-to-point environments.
DQS# ENABLE/DISABLE
The DQS# ball is enabled by bit E10. When E10 = 0, DQS# is
the complement of the differential data strobe pair DQS/DQS#.
When disabled (E10 = 1), DQS is used in a single ended mode
and the DQS# ball is disabled. When disabled, DQS# should be
left oating. This function is also used to enable/disable RDQS#. If
RDQS is enabled (E11 = 1) and DQS# is enabled (E10 = 0), then
both DQS# and RDQS# will be enabled.
OUTPUT ENABLE/DISABLE
The OUTPUT ENABLE function is dened by bit E12, as shown in
Figure 7. When enabled (E12 = 0), all outputs (DQs, DQS, DQS#,
RDQS, RDQS#) function normally. When disabled (E12 = 1), all
DDR2 SDRAM outputs (DQs, DQS, DQS#, RDQS, RDQS#) are
disabled, thus removing output buffer current. The output disable
feature is intended to be used during ICC characterization of read
current.
ON-DIE TERMINATION (ODT)
ODT effective resistance, RTT (EFF), is dened by bits E2 and E6
of the EMR, as shown in Figure 7. The ODT feature is designed
to improve signal integrity of the memory channel by allowing the
DDR2 SDRAM controller to independently turn on/off ODT for
any or all devices. RTT effective resistance values of 50Ω ,75Ω,
and 150Ω are selectable and apply to each DQ, DQS/DQS#,
RDQS/RDQS#, UDQS/UDQS#, LDQS/LDQS#, DM, and UDM/
LDM signals. Bits (E6, E2) determine what ODT resistance is
enabled by turning on/off “sw1,” “sw2,” or “sw3.” The ODT effective
resistance value is elected by enabling switch “sw1,” which enables
all R1 values that are 150Ω each, enabling an effective resistance
of 75Ω (RTT2(EFF) = R2/2). Similarly, if “sw2” is enabled, all R2
values that are 300Ω each, enable an effective ODT resistance
of 150Ω (RTT2(EFF) = R2/2). Switch “sw3” enables R1 values of
100Ω enabling effective resistance of 50Ω Reserved states should
not be used, as unknown operation or incompatibility with future
versions may result.
The ODT control ball is used to determine when RTT(EFF) is turned
on and off, assuming ODT has been enabled via bits E2 and E6 of
A9
A7 A 6 A5 A4 A3
A8
A2
A1 A0
Extended Mo de
Register (Ex)
Address Bus
97
6
5
4
3
82
1
0
A10
A12 A11
BA0
BA1
BA2
10
11
12
13
01
14
1
16
5
A13
0
1
0
1
Mode Register Definition
Mo de Register (MR)
Extended Mo de Register (EMR)
Extended Mo de Register (EMR2)
Extended Mo de Register (EMR3)
M15
0
1
M14
EMR2
01
01 01
01
High Temperature Self Refresh rate enable
Commer cial-Temperature default
Industrial-Temperature option;
use if TC exceeds 85°C
E7
0
1
FIGURE 8 – EXTENDED MODE REGISTER 2 (EMR2) DEFINITION
Note: 1. E13 (A13)-E0(A0) are reserved for future use and must be programmed to "0." A13 is not used in this device.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
W3H32M72E-400SBC 制造商:Microsemi Corporation 功能描述:32M X 72 DDR2, 1.8V, 400MHZ, 208PBGA COMMERICAL TEMP. - Bulk
W3H32M72E-400SBI 制造商:Microsemi Corporation 功能描述:32M X 72 DDR2, 1.8V, 400MHZ, 208PBGA INDUSTRIAL TEMP. - Bulk
W3H32M72E-400SBM 制造商:Microsemi Corporation 功能描述:32M X 72 DDR2, 1.8V, 400MHZ, 208PBGA MIL-TEMP. - Bulk
W3H32M72E-533ES 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:32M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package
W3H32M72E-533ESC 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:32M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package
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