參數(shù)資料
型號(hào)： VSP2265
英文描述： 10-Bit. 25 Msps CCD Signal Processor for Digital Cameras with V/H Timing Generator
中文描述： 10位。 25 Msps的CCD信號(hào)處理器為數(shù)碼相機(jī)與V /小時(shí)時(shí)序發(fā)生器
文件頁(yè)數(shù)： 9/87頁(yè)
文件大小： 1303K
代理商： VSP2265
Introduction
4
SLES056
—
December 2002
VSP2265
1.6
Terminal Functions
TERMINAL
TYPE
DESCRIPTIONS
NAME
NO.
ADCCK
J2
DO
Clock for digital output buffer
B0
J6
DO
A/D converter output, bit 0
B1
J5
DO
A/D converter output, bit 1
B2
K5
DO
A/D converter output, bit 2
B3
H5
DO
A/D converter output, bit 3
B4
K4
DO
A/D converter output, bit 4
B5
J4
DO
A/D converter output, bit 5
B6
H4
DO
A/D converter output, bit 6
B7
K3
DO
A/D converter output, bit 7
B8
J3
DO
A/D converter output, bit 8
B9
H3
DO
A/D converter output, bit 9
Internal reference C (bypass to ground)
Internal reference P (bypass to ground)
§
Internal reference N (bypass to ground)
BYP
A2
AO
BYP2
A1
AO
BYPM
B1
AO
CCDIN
A4
AI
CCD signal input
CH1
J9
DO
Readout pulse 1
CH2
K10
DO
Readout pulse 2
CH3
J10
DO
Readout pulse 3
CH4
H9
DO
Readout pulse 4
CLKO
C7
DO
FCK output
A/D converter common-mode voltage (bypass to ground)
CM
C1
AO
COB
B2
AO
Optical black clamp loop reference (bypass to ground)
H1
B10
DO
CCD horizontal driver 1
H2
D8
DO
CCD horizontal driver 2
HD
H7
DI
HD input
MCLK
C6
DI
Master clock input
NC
A3, B3, C4, D3, D4,
D5, D6, D7, E4, E7,
F4, F7, F8, G2, G4,
G5, G6, G7, K1, K2
—
R
E8
DO
CCD reset driver
A/D converter negative voltage (bypass to ground)
A/D converter positive voltage (bypass to ground)
REFN
D2
AO
REFP
D1
AO
SCLK
H2
DI
Clock for serial-data shift
SDATA
H1
DI
Serial-data input
SLOAD
G3
DI
Serial-data latch signal
SOUT
J1
DO
Serial-data monitor out
STO
F10
DO
Strobe
SUB
E9
DO
CCD sub pulse
SUBSW
F9
DO
CCD sub bias control
Designators in TYPE column: P
–
Power supply and ground, DI
–
Digital input, DO
–
Digital output, AI
–
Analog input, AO
–
Analog output
Should be connected to ground with a bypass capacitor. A value of 0.1
μ
F to 0.22
μ
F is recommended; however, it depends on the application
environment. See the
Black Level Clamp Loop and 10-Bit DAC
(Section 2.9) for details.
§
Should be connected to ground with a bypass capacitor. A value of 400 pF to 1000 pF is recommended; however, it depends on the application
environment. See
Voltage Reference
(Section 2.13) for details.
Should be connected to ground with a bypass capacitor (0.1
μ
F). See
Voltage Reference
(Section 2.13) for details.
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