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參數資料
| 型號： | VSP2265 |
| 英文描述： | 10-Bit. 25 Msps CCD Signal Processor for Digital Cameras with V/H Timing Generator |
| 中文描述： | 10位。 25 Msps的CCD信號處理器為數碼相機與V /小時時序發(fā)生器 |
| 文件頁數： | 24/87頁 |
| 文件大小： | 1303K |
| 代理商： | VSP2265 |
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Theory of Operation
20
SLES056
—
December 2002
VSP2265
2.17 Still Function
2.17.1
Operation Outline
Readout timing is selected by the TRG input. Smear dump operation, which is synchronized to the mechanical
shutter, is available.
SUB output is controlled by using both the serial data instruction and the external TRG signal.
The SUBSW level follows the still mode condition. SUBSW can be used for the SUB bias control circuit when
using a mechanical shutter. It is recommended to set the toggling position of SUBSW after the mechanical
shutter has closed.
2.17.2
Operation Sequence
1.
Set the serial data address 000101.
Input bit 2 = H, and set to the still mode.
Select the trigger signal EDGSL bit 3 = L for VD or bit 3 = H for TRG.
Select the SUB output STLSUB bit 4 = L for TRG input or bit 4 = H for serial data input.
(In this case, the SUB output is defined by the TRG input. To use the serial data instruction, the integration
time is defined by ES 000111, which can be done after Step 2, following.)
2.
Input a pulse to SLOAD and send the serial data.
3.
Set the serial data address 001010. Input the STVV data in bits 0
–
5 for SUBSW rise time definition. Data
is stored in the register 1 H before a readout operation. Upon going to still mode, during the horizontal scan
time preceding a readout operation, a SUB output is made for every H and charge is drained.
4.
Input a TRG falling edge signal if necessary. The TRG falling edge is latched by the internal HD_flg. The
SUB output goes high after the next horizontal blank, and charge integration starts. See Note 1.
5.
Input a TRG rising edge or VD signal. SUBSW goes high at the position defined by the serial data. The
SUBSW toggling position is determined by counting the number of HD pulses after the rising edge of TRG
or VD. A vertical high-speed pulse, which is more than the the line number of one field, is applied.
6.
Input serial data to set bit 3 = L at address 000101 and release the the trigger-select function during the
vertical high-speed pulse operation that was initiated in Step 5.
7.
Input a VD pulse after one field of CCD output signal has completed, keeping SUBSW high.
8.
Input serial data for address 000101 and bit 2 = L to exit from the still mode.
9.
Input a VD pulse after one field of CCD output signal has completed. SUBSW goes low at the next HD
rising edge.
NOTES:
1. In this mode, the mechanical shutter was open while the TRG input was low.
2. Do n
o
t use the electronic shutter in the still mode, when SUBSW is high.
3. For the VD-to-VD interval, more than 90 counts of the HD-to-HD interval are required.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| VSP2265GSJ | 功能描述:IC CCD SIGNAL PROCESSOR 96-BGA RoHS:是 類別:集成電路 (IC) >> 線性 - 視頻處理 系列:- 產品變化通告:Product Discontinuation 07/Mar/2011 標準包裝:3,000 系列:OMNITUNE™ 類型:調諧器 應用:移動電話，手機，視頻顯示器 安裝類型:表面貼裝 封裝/外殼:65-WFBGA 供應商設備封裝:PG-WFSGA-65 包裝:帶卷 (TR) 其它名稱:SP000365064 |
| VSP2265GSJR | 功能描述:視頻 IC 10-Bit 25 Msps Signal Processor RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| VSP2265ZSJR | 功能描述:視頻 IC 10B 25Msps CCD Sig Proc RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| VSP2265ZSJRG1 | 功能描述:視頻 IC 10B 25Msps CCD Sig Proc RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| VSP2267 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:CCD Singnal Processor with Timing Generator for Digital cameras |
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