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參數(shù)資料
| 型號(hào)： | VSP2265 |
| 英文描述： | 10-Bit. 25 Msps CCD Signal Processor for Digital Cameras with V/H Timing Generator |
| 中文描述： | 10位。 25 Msps的CCD信號(hào)處理器為數(shù)碼相機(jī)與V /小時(shí)時(shí)序發(fā)生器 |
| 文件頁(yè)數(shù)： | 19/87頁(yè) |
| 文件大?。?/td> | 1303K |
| 代理商： | VSP2265 |
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Theory of Operation
15
SLES056
—
December 2002
VSP2265
2.11 Power-Save Mode
For the purpose of power savings, the VSP2265 can be put into the standby plus power-save mode by serial
interface command. In this mode, all the function blocks are disabled, the A/D outputs all go to zero and the
TG output goes to high or low status by configuration of the serial interface command. The current
consumption drops to 34 mA. Because all the bypass capacitors discharge during this mode, a substantial
time (usually of the order of 200
–
300 ms) is required to restore from the standby plus power-save mode.
2.12 Additional Output Delay Control
The VSP2265 can control the delay time of output data by setting registers through the serial interface. In some
cases, the transition of output data affects analog performance. Generally, this is avoided by adjusting the
timing of ADCCK. In case the ADCCK timing cannot be adjusted, the additional output delay control is effective
for reducing the influence of transient noise. Refer to the
Serial Interface Timing Specification
(Section 3)for
details.
2.13 Voltage Reference
All the reference voltages and bias currents used on the device are created from internal band-gap circuitry.
The CDS and the ADC mainly use three reference voltages, REFP (1.75 V), REFN (1.25 V) and CM (1.5 V).
REFP and REFN are buffered on-chip. CM is derived as the midvoltage of the resistor chain connecting REFP
and REFN internally. The ADC full-scale range is determined by twice the voltage difference between REFP
and REFN.
REFP, REFN, and CM should be heavily decoupled with appropriate capacitors.
Table 2
–
1. Function Table
OPERATION MODE
FUNCTION
2A CCD
×
2 SPEED
2B CCD
×
2 SPEED
FIELD
√
√
√
√
√
√
√
FRAME
√
√
√
√
√
√
√
×
2 MONITOR
√
√
√
√
√
√
√
FIELD
√
√
√
√
√
√
√
FRAME
√
√
√
√
√
√
√
×
2 MONITOR
√
√
√
√
√
√
√
LONG INTEGRATION (CHDEL)
√
√
√
√
√
√
√
√
√
√
√
√
√
√
POWER SAVE (PWSV)
STROBE (STRB)
STILL (STIL)
E-ZOOM (EZOOM)
E-SHUTTER
SUB STOP 1/4-STEP
Recommended CCD MN39470, MN39472, MN39473 (Panasonic)
Recommended CCD MN39471, MN39474 (Panasonic)
2.14 Operating Modes
Field mode enables the summation of vertically neighboring pixels.
Frame mode enables each pixel output.
×
2 speed mode enables output interval lines.
×
2 monitor mode enables output of two by eight lines or two by ten lines for CCDs 2A or 2B, respectively.
The field mode, frame mode, and
×
2 speed mode operate with interlace between even/odd frames.
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