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參數(shù)資料
| 型號： | VSP2265 |
| 英文描述： | 10-Bit. 25 Msps CCD Signal Processor for Digital Cameras with V/H Timing Generator |
| 中文描述： | 10位。 25 Msps的CCD信號處理器為數(shù)碼相機與V /小時時序發(fā)生器 |
| 文件頁數(shù)： | 15/87頁 |
| 文件大?。?/td> | 1303K |
| 代理商： | VSP2265 |
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Theory of Operation
11
SLES056
—
December 2002
VSP2265
2.3
Analog Front End
Figure 2
–
5 shows a simplified AFE block diagram of the VSP2265. The AFE circuit includes the correlated
double sampler (CDS), a 14-bit analog-to-digital converter (ADC), digital gain amplifier, black-level clamp
loop, input clamp, CDS timing generator, and voltage reference. An off-chip emitter-follower buffer or
preamplifier is needed between the CCD output and the VSP2265 CCDIN input.
Output
Register
Input Clamp
14-Bit
ADC
CDS
10-Bit
Output
Decoder
10-Bit
DAC
CCD
Input
PBLK
CPOB
CLPD
SYSRST
ADCCK
CLPOB
ADCCK
SYSRST
On Chip
Off Chip
Figure 2
–
5. VSP2265 AFE Simplified Block Diagram
2.4
Correlated Double Sampler (CDS)
The output signal of a CCD image sensor is sampled twice during one pixel period: once during the reference
interval and again during the data interval. Subtracting these two samples extracts the video information of
the pixel and removes noise which is low frequency
—
the kTC and CCD reset noise. Figure 2
–
6 is a block
diagram of the CDS.
The CDS is driven through an off-chip coupling capacitor C
IN.
(A 0.1-
μ
F capacitor is recommended for C
IN
).
AC coupling is highly recommended because the dc level of the CCD output signal is usually too high (several
volts) for the CDS to work properly. The appropriate common-mode voltage for the CDS is around 0.5 V
–
1.5 V.
The reference-level sampling is performed while SHP is active, and the voltage level is held on sampling
capacitor C
1
at the trailing edge of SHP. The data-level sampling is performed while SHD is active, and the
voltage level is held on sampling capacitor C
2
at the trailing edge of SHD. Then the subtraction of the two levels
is performed by the switched-capacitor amplifier. The off-chip emitter follower or equivalent buffer must be able
to drive more than 10 pF because the 10-pF sampling capacitor is seen at the input terminal. (Usually
additional stray capacitance of a few pF is present.) The analog input signal range of the VSP2265 is about
1 Vp-p.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| VSP2265GSJ | 功能描述:IC CCD SIGNAL PROCESSOR 96-BGA RoHS:是 類別:集成電路 (IC) >> 線性 - 視頻處理 系列:- 產(chǎn)品變化通告:Product Discontinuation 07/Mar/2011 標準包裝:3,000 系列:OMNITUNE™ 類型:調諧器 應用:移動電話，手機，視頻顯示器 安裝類型:表面貼裝 封裝/外殼:65-WFBGA 供應商設備封裝:PG-WFSGA-65 包裝:帶卷 (TR) 其它名稱:SP000365064 |
| VSP2265GSJR | 功能描述:視頻 IC 10-Bit 25 Msps Signal Processor RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| VSP2265ZSJR | 功能描述:視頻 IC 10B 25Msps CCD Sig Proc RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| VSP2265ZSJRG1 | 功能描述:視頻 IC 10B 25Msps CCD Sig Proc RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| VSP2267 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:CCD Singnal Processor with Timing Generator for Digital cameras |
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