參數資料
型號: VSP2265
英文描述: 10-Bit. 25 Msps CCD Signal Processor for Digital Cameras with V/H Timing Generator
中文描述: 10位。 25 Msps的CCD信號處理器為數碼相機與V /小時時序發(fā)生器
文件頁數: 41/87頁
文件大?。?/td> 1303K
代理商: VSP2265
Serial Interface Timing Specification
38
SLES056
December 2002
VSP2265
3.1.19
ADCCK Register
SD15
SD14
SD13
SD12
SD1
1
SD1
0
SD9
SD8
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
0
1
0
1
1
0
ADCCK
ext
ADCCK
mon
0
0
ADCCK90
MSB
ADCCK90
LSB
ADCCKri3
MSB
ADCCKri2
ADCCKri1
ADCCKri0
LSB
default
0
1
0
0
0
1
0
1
0
0
BIT
NAME
DEFAULT VALUE
DESCRIPTION
SD9
ADCCK ext
0
External selection:
0 = Without use of external ADCCK-clock
1 = Use external ADCCK-clock
SD8
ADCCK mon
1
Monitor selection:
0 = ADCCK-clock monitor
1 = ADCCK-clock without monitor
ADCLK 90
°
adjustment:
00 = ADCCK phase is lagging 0
°
with respect to CLKO
01 = ADCCK phase is lagging 90
°
with respect to CLKO
10 = ADCCK phase is lagging 180
°
with respect to CLKO
11 = ADCCK phase is lagging 270
°
with respect to CLKO
SD5
SD4
ADCCK90[1:0]
01
SD3
SD0
ADCCKri[3:0]
0100
ADCLK delay edge definition using 4 bits
3.1.20
Test AFE I/O Register
SD15
SD14
SD13
SD12
SD11
SD10
SD9
SD8
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
0
1
1
0
0
0
TP23
MSB
TP23
TP23
LSB
TP01
CLPDM
ext
0
PBLK
ext
0
CLPOB
ext
0
default
0
0
0
0
0
0
0
0
0
0
BIT
NAME
DEFAULT VALUE
DESCRIPTION
SD9
SD7
TP23[2:0]
000
TP23 input source selection:
000 = open
001 = SHP and SHD
110 = CLPOB and CLPDM
111 = PBLK and CLPDM
SD6
TP01
0
TP01 source selection:
0 = H1 and R
1 = H1 and H2
SD5
CLPDM
ext
0
CLPDM input source selection:
0 = Use internally generated CLPDM clock, with or without monitor
1 = Use external CLPDM clock
SD3
PBLK
ext
0
PBLK input source selection:
0 = Use internally generated PBLK clock, with or without monitor
1 = Use external PBLK clock
SD1
CLPOB
ext
0
CLPOB input source selection:
0 = Use internally generated CLPOB clock, with or without monitor
1 = Use external CLPOB clock
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