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參數(shù)資料
| 型號： | VSP2265 |
| 英文描述： | 10-Bit. 25 Msps CCD Signal Processor for Digital Cameras with V/H Timing Generator |
| 中文描述： | 10位。 25 Msps的CCD信號處理器為數(shù)碼相機與V /小時時序發(fā)生器 |
| 文件頁數(shù)： | 18/87頁 |
| 文件大小： | 1303K |
| 代理商： | VSP2265 |
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Theory of Operation
14
SLES056
—
December 2002
VSP2265
2.9
Black-Level Clamp Loop and 10-Bit DAC
To extract the video information correctly, the CCD signal must be referenced to a well-established black level.
The VSP2265 has an auto-zero loop (calibration loop) to establish the black level using the CCD optical black
(OB) pixels. Figure 2
–
8 shows the block diagram of this loop. The input signal level from the OB pixels is
identified as the real black level, and the loop is closed during this period (actually during the period while
CPOB = ACTIVE). While the auto-zero loop is closed, the difference between the ADC output code is
evaluated and applied to the decoder, which then controls the 10-bit current DAC. The current DAC can charge
or discharge the external capacitor at COB, depending on the sign of the code difference. The loop adjusts
the voltage at COB, which sets the offset of the CDS to make the code difference zero. Thus the ADC output
code converges to black level during CPOB = ACTIVE and maintains the black level derived from the OB pixels
after the loop has converged. CPOB performs the OB clamping of both channels simultaneously.
To determine the loop time constant, an off-chip capacitor is required and should be connected to the COB
terminal. The time constant T is calculated using the following equation:
T
C
(16384
I
MIN
)
where C is the capacitor value connected to COB, I
MIN
is the minimum current (0.15
μ
A) of the control DAC
in the OB level clamp loop, and 0.15
μ
A is equivalent to 1 LSB of the DAC output current. When C is 0.1
μ
F,
then the time constant T is 40.7
μ
s for the ADC output code from 0 LSB to 1543 LSB (The convergence curve
becomes exponential).
For the output code above 1543 LSB, the current DAC injects constant (maximum) current into the capacitor
and the convergence curve becomes linear. The slew rate SR is calculated using the following equation.
SR
I
MAX
C
where C is the capacitor value connected to COB. I
MAX
is the maximum current (153
μ
A) of the control DAC
in the OB level clamp loop, and 153
μ
A is equivalent to 1023 LSB of the DAC output current.
Generally, OB level clamping at high speed causes clamping noise. However, the noise can be reduced by
making C large. On the other hand, a large C requires a much longer time to restore from the power-save mode
or right after the power goes ON. Therefore, 0.1
μ
F to 0.22
μ
F is considered a reasonable value for C. If the
application environment requires a value outside this range, making careful adjustments by the trial-and-error
method is recommended.
The OB clamp level (the pedestal level) is programmable through the serial interface; see the
Serial Interface
Timing Specification
(Section 3) for details. Also see the
Serial Interface Timing Specification
section for the
relationship between input code and the OB clamp level.
The black-level clamp loop not only eliminates the CCD black-level offset, but also eliminates the offsets of
the VSP2265 CDS and ADC themselves.
2.10 Preblanking and Data Latency
The VSP2265 has a preblanking function. When PBLK = LOW, the digital outputs all become zero at the ninth
rising edge of ADCCK, counting from the time when PBLK becomes LOW, to accommodate the clock latency
of the VSP2265.
Data latency of this device is seven clock cycles. The digital output data come out on the rising edge of ADCCK
with a delay of seven clock cycles.
Some CCDs have a large transient output signal during blanking intervals. If the input voltage is higher than
the supply rail or lower than the ground rail by 0.3 V, then protection diodes are turned on, limiting the input
voltage. Such a high-swing signal can cause device damage to the VSP2265 and should be avoided.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| VSP2265GSJ | 功能描述:IC CCD SIGNAL PROCESSOR 96-BGA RoHS:是 類別:集成電路 (IC) >> 線性 - 視頻處理 系列:- 產(chǎn)品變化通告:Product Discontinuation 07/Mar/2011 標準包裝:3,000 系列:OMNITUNE™ 類型:調(diào)諧器 應(yīng)用:移動電話，手機，視頻顯示器 安裝類型:表面貼裝 封裝/外殼:65-WFBGA 供應(yīng)商設(shè)備封裝:PG-WFSGA-65 包裝:帶卷 (TR) 其它名稱:SP000365064 |
| VSP2265GSJR | 功能描述:視頻 IC 10-Bit 25 Msps Signal Processor RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| VSP2265ZSJR | 功能描述:視頻 IC 10B 25Msps CCD Sig Proc RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| VSP2265ZSJRG1 | 功能描述:視頻 IC 10B 25Msps CCD Sig Proc RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| VSP2267 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:CCD Singnal Processor with Timing Generator for Digital cameras |
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