
CHAPTER 17 INTERRUPT FUNCTIONS
User’s Manual U19678EJ1V1UD
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Figure 17-2. Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H) (2/2)
Address: FFFD1H
After reset: 00H
R/W
Symbol
7
6
5
4
3
<2>
<1>
<0>
IF2H
0
TMIF11
TMIF10
TMIF09
XXIFX
Interrupt request flag
0
No interrupt request signal is generated
1
Interrupt request is generated, interrupt request status
Notes 1. CSIIF01 and CSIIF00 bits are not provided in the 78K0R/IB3 and the 38-pin products of the 78K0R/IC3.
2. IICAIF bit is not provided in the 78K0R/IB3 and the 38-pin and 44-pin products of the 78K0R/IC3. In
these products, be sure to set bit 3 of the IF1L register to 0.
3. Those bits are not provided in the 78K0R/IB3. In the case of 78K0R/IB3, be sure to set bits 1 and 2 of
the IF1H register, and bits 3 and 4 of the IF2L register to 0.
Cautions 1.
Be sure to clear the following bits to 0.
78K0R/IB3
: Bit 3 of IF1L, Bits 1 to 3 of IF1H, Bits 3 and 4 of
IF2L, and Bits 3 to 7 of IF2H
38-pin and 44-pin products of 78K0R/IC3 : Bit 3 of IF1L, Bit 3 of IF1H, and Bits 3 to 7 of
IF2H
48-pin products of 78K0R/IC3, 78K0R/ID3,
78K0R/IE3
: Bit 3 of IF1H and Bits 3 to 7 of IF2H
2.
When operating a timer, serial interface, or A/D converter after standby release, operate it
once after clearing the interrupt request flag. An interrupt request flag may be set by noise.
3.
When manipulating a flag of the interrupt request flag register, use a 1-bit memory
manipulation instruction (CLR1). When describing in C language, use a bit manipulation
instruction such as “IF0L.0 = 0;” or “_asm(“clr1 IF0L, 0”);” because the compiled assembler
must be a 1-bit memory manipulation instruction (CLR1).
If a program is described in C language using an 8-bit memory manipulation instruction
such as “IF0L &= 0xfe;” and compiled, it becomes the assembler of three instructions.
mov a, IF0L
and a, #0FEH
mov IF0L, a
In this case, even if the request flag of another bit of the same interrupt request flag
register (IF0L) is set to 1 at the timing between “mov a, IF0L” and “mov IF0L, a”, the flag is
cleared to 0 at “mov IF0L, a”.
Therefore, care must be exercised when using an 8-bit
memory manipulation instruction in C language.
(2) Interrupt mask flag registers (MK0L, MK0H, MK1L, MK1H, MK2L, MK2H)
The interrupt mask flags are used to enable/disable the corresponding maskable interrupt servicing.
MK0L, MK0H, MK1L, MK1H, MK2L, and MK2H can be set by a 1-bit or 8-bit memory manipulation instruction.
When MK0L and MK0H, MK1L and MK1H, and MK2L and MK2H are combined to form 16-bit registers MK0,
MK1, and MK2, they can be set by a 16-bit memory manipulation instruction.
Reset signal generation sets these registers to FFH.
Remark
If an instruction that writes data to this register is executed, the number of instruction execution clocks
increases by 2 clocks.