CHAPTER 6 TIMER ARRAY UNIT TAUS
User’s Manual U19678EJ1V1UD
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6.7.5 Operation as input signal high-/low-level width measurement
Caution When using a channel to implement the LIN-bus, set bit 1 (ISC1) of the input switch control
register (ISC) to 1. RxD0 signal will be input to the channel 7.
Also, when RxD0 functions alternately as a timer input pin, the corresponding timer input pin
channels can also be used for the LIN-bus function. The timer channels in each version of
the 78K0R/Ix3 that can be used for the LIN-bus function in addition to timer channel 7 are
shown below.
78K0R/IB3 (P11/RxD0/TI03/TO03)
: Channel 3 of TAUS
38-pin products of 78K0R/IC3 (P72/INTP6/RxD0)
: None
44-pin and 48-pin products of 78K0R/IC3, 78K0R/ID3,
78K0R/IE3 (P74/RxD0/TI10/SI00)
: Chanel 10 of TAUS
When using a channel to implement the LIN-bus, Read “TIn” as “RxD0” in the following
description.
By starting counting at one edge of TIn and capturing the number of counts at another edge, the signal width (high-
level width/low-level width) of TIn can be measured.
The signal width of TIn can be calculated by the following
expression.
Signal width of TIn input = Period of count clock
× ((10000H × TSRn: OVF) + (Capture value of TDRn + 1))
Caution The TIn pin input is sampled using the operating clock selected with the CKSn bit of the
TMRn register, so an error equivalent to one operation clock occurs.
TCRn operates as an up counter in the capture & one-count mode.
When the channel start trigger (TSn) of the timer channel start register 0 (TS0) is set to 1, TEn is set to 1 and the
TIn pin start edge detection wait status is set.
When the TIn start edge (rising edge of TIn pin input when the high-level width is to be measured) is detected, the
counter counts up from 0000H in synchronization with the count clock. When the valid capture edge (falling edge of
TIn when the high-level width is to be measured) is detected later, the count value is transferred to TDRn and, at the
same time, INTTMn is output. If the counter overflows at this time, the OVF bit of the TSRn register is set to 1. If the
counter does not overflow, the OVF bit is cleared. TCRn stops at the value “value transferred to TDRn + 1”, and the
TIn pin start edge detection wait status is set. After that, the above operation is repeated.
At the same time that the count value is captured to the TDRn register, the OVF bit of the TSRn register is updated
depending on whether the counter overflows during the measurement period. Therefore, the overflow status of the
captured value can be checked.
If the counter reaches a full count for two or more periods, it is judged to be an overflow occurrence, and the OVF
bit of the TSRn register is set to 1.
However, the correct value of high/low level width cannot be measured for the
OVF bit, if two or more overflows occur.
Whether the high-level width or low-level width of the TIn pin is to be measured can be selected by using the CISn1
and CISn0 bits of the TMRn register.
Because this function is used to measure the signal width of the TIn pin input, TSn cannot be set to 1 while TEn is
1.
CISn1, CISn0 of TMRn = 10B: Low-level width is measured.
CISn1, CISn0 of TMRn = 11B: High-level width is measured.
Remark
n = 00 to 11 (78K0R/IB3: n = 02 to 07 and 09)