CHAPTER 3 CPU ARCHITECTURE
User’s Manual U19678EJ1V1UD
99
Figure 3-3. Memory Map (
μ PD78F1214, 78F1224, 78F1234)
Data memory
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Program
memory
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00000H
EFFFFH
F0000H
F0FFFH
F1000H
FC000H
FBFFFH
FF6FFH
FF700H
FFEDFH
FFEE0H
FFEFFH
FFF00H
FFFFFH
0BFFFH
0C000H
F07FFH
F0800H
00000H
0007FH
00080H
000BFH
000C0H
000C3H
000C4H
00FFFH
01000H
0107FH
01080H
010BFH
010C0H
010C3H
010C4H
0BFFFH
Vector table area
128 bytes
CALLT table area
64 bytes
Program area
Option byte areaNote 3
4 bytes
Vector table area
128 bytes
CALLT table area
64 bytes
Option byte areaNote 3
4 bytes
Program area
On-chip debug security
ID setting areaNote 3
10 bytes
01FFFH
Boot cluster 0Note 4
Boot cluster 1
010CDH
010CEH
On-chip debug security
ID setting areaNote 3
10 bytes
000CDH
000CEH
Special function register (SFR)
256 bytes
General-purpose register
32 bytes
RAMNotes 1, 2
2 KB
Mirror
44 KB
Reserved
Special function register (2nd SFR)
2 KB
Reserved
Flash memory
48 KB
Notes 1. Use of the area FFE20H to FFEDFH is prohibited when using the self-programming function. Since this
area is used for self-programming library.
2. Instructions can be executed from the RAM area excluding the general-purpose register area.
3. When boot swap is not used: Set the option bytes to 000C0H to 000C3H, and the on-chip debug
security IDs to 000C4H to 000CDH.
When boot swap is used:
Set the option bytes to 000C0H to 000C3H and 010C0H to 010C3H, and
the on-chip debug security IDs to 000C4H to 000CDH and 010C4H to
010CDH.
4. Writing boot cluster 0 can be prohibited depending on the setting of security (see 24.7
Security
Setting).