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CHAPTER 6 TIMER ARRAY UNIT TAUS
User’s Manual U19678EJ1V1UD
330
Figure 6-47. Operation Procedure When Frequency Divider Function Is Used
Software Operation
Hardware Status
Power-off status
(Clock supply is stopped and writing to each register is
disabled.)
Sets the TAU0EN bit of the PER2 register to 1.
Power-on status. Each channel stops operating.
(Clock supply is started and writing to each register is
enabled.)
TAUS
default
setting
Sets the TPS0 register.
Determines the clock frequencies of CK00 and CK01
for channels 0 to 7, and those of CK02 and CK03 for
channels 8 to 11.
Sets the TMRn register (determines the operation mode
of the channel and selects the detection edge).
Sets interval (period) value to the TDRn register.
Channel stops operating.
(Clock is supplied and some power is consumed.)
Channel
default
setting
Clears the TOMn bit of the TOM0 register to 0 (master
channel output mode).
Clears the TOLn bit to 0.
Sets the TOn bit and determines default level of the TOn
output.
Sets TOEn to 1 and enables operation of TOn.
Clears the port register and port mode register to 0.
The TOn pin goes into Hi-Z output state.
The TOn default setting level is output when the port mode
register is in output mode and the port register is 0.
TOn does not change because channel stops operating.
The TOn pin outputs the TOn set level.
Operation
start
Sets the TOEn to 1 (only when operation is resumed).
Sets the TSn bit to 1.
The TSn bit automatically returns to 0 because it is a
trigger bit.
TEn = 1, and count operation starts.
Value of TDRn is loaded to TCRn at the count clock input.
INTTMn is generated and TOn performs toggle operation if
the MDn0 bit of the TMRn register is 1.
During
operation
Set value of the TDRn register can be changed.
The TCRn register can always be read.
The TSRn register is not used.
Set values of TO0 and TOE0 registers can be changed.
Set values of TMRn register, TOMn, and TOLn bits
cannot be changed.
Counter (TCRn) counts down. When count value reaches
0000H, the value of TDRn is loaded to TCRn again, and the
count operation is continued. By detecting TCRn = 0000H,
INTTMn is generated and TOn performs toggle operation.
After that, the above operation is repeated.
The TTn bit is set to 1.
The TTn bit automatically returns to 0 because it is a
trigger bit.
TEn = 0, and count operation stops.
TCRn holds count value and stops.
The TOn output is not initialized but holds current status.
Operation
stop
TOEn is cleared to 0 and value is set to the TO0n bit.
The TOn pin outputs the TOn set level.
To hold the TOn pin output level
Clears TOn bit to 0 after the value to
be held is set to the port register.
When holding the TOn pin output level is not
necessary
Switches the port mode register to input mode.
The TOn pin output level is held by port function.
The TOn pin output level goes into Hi-Z output state.
TAUS
stop
The TAU0EN bit of the PER2 register is cleared to 0.
Power-off status
All circuits are initialized and SFR of each channel is also
initialized.
(The TOn bit is cleared to 0 and the TOn pin is set to port
mode).
Remark
n = 00, 10, 11 (44-pin and 48-pin products of 78K0R/IC3: n = 10 and 11)
Oper
ation
is
re
su
med.