參數(shù)資料
型號: uPD720114GA-YEU-A
廠商: NEC Corp.
英文描述: MOS INTEGRATED CIRCUIT
中文描述: 馬鞍山集成電路
文件頁數(shù): 6/32頁
文件大?。?/td> 269K
代理商: UPD720114GA-YEU-A
Data Sheet S17462EJ4V0DS
6
μ
PD720114
1.
PIN INFORMATION
Pin Name
I/O
Buffer Type
Active
Level
Function
X1
I
2.5 V input
30 MHz Crystal oscillator in
X2
O
2.5 V output
30 MHz Crystal oscillator out
SYSRSTB
I
3.3 V Schmitt input
Low
Asynchronous chip hardware reset
DP(4:1)
I/O
USB D
+
signal I/O
USB’s downstream facing port D
+
signal
DM(4:1)
I/O
USB D
signal I/O
USB’s downstream facing port D
signal
DPU
I/O
USB D
+
signal I/O
USB’s upstream facing port D
+
signal
DMU
I/O
USB D
signal I/O
USB’s upstream facing port D
signal
BUS_B
I
3.3 V Schmitt input
Power mode select
RREF
A (O)
Analog
Reference resistor connection
CSB1
I
5 V tolerant Schmitt input
Low
Port’s over-current status input.
CSB(4:2)
I
3.3 V Schmitt input
Low
Port’s over-current status input
PPB(4:1)
I/O
3.3 V output / input
Low
Port’s power supply control output or hub
configuration input
VBUSM
I
5 V tolerant Schmitt input
Upstream V
BUS
monitor
AMBER
I/O
3.3V output / input
Amber colored LED control output or port
indicator select
GREEN
O
3.3V output
Green colored LED control output or port
indicator select
LED(4:1)
I/O
3.3V output / input
Low
LED indicator output show downstream port
status or Removable/Non-removable select
TEST
I
3.3 V Schmitt input
Test signal
V
DD25OUT
On chip 2.5 V regulator output, it must have a
4.7
μ
F (or greater) capacitor to V
SSREG
V
DD33
3.3 V V
DD
V
DD33REG
3.3 V V
DD
for on chip 2.5 V regulator input, it must
have a 4.7
μ
F ( or greater) capacitor to V
SSREG
V
DD25
2.5 V V
DD
AV
DD
2.5 V V
DD
for analog circuit
V
SS
V
SS
V
SSREG
On chip 2.5 V regulator V
SS
AV
SS
V
SS
for analog circuit
AV
SS
(R)
V
SS
for reference resistor, Connect to AV
SS
.
Remark
“5 V tolerant“ means that the buffer is 3 V buffer with 5 V tolerant circuit.
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