參數(shù)資料
型號(hào)： uPD720114GA-YEU-A
廠商： NEC Corp.
英文描述： MOS INTEGRATED CIRCUIT
中文描述： 馬鞍山集成電路
文件頁(yè)數(shù)： 3/32頁(yè)
文件大?。?/td> 269K
代理商： UPD720114GA-YEU-A
Data Sheet S17462EJ4V0DS
3
μ
PD720114
APLL
ALL_TT
: Generates all clocks of Hub.
: Translates the high-speed transactions (split transactions) for full/low-speed device
to full/low-speed transactions. ALL_TT buffers the data transfer from either
upstream or downstream direction. For OUT transaction, ALL_TT buffers data from
upstream port and sends it out to the downstream facing ports after speed
conversion from high-speed to full/low-speed. For IN transaction, ALL_TT buffers
data from downstream ports and sends it out to the upstream facing ports after
speed conversion from full/low-speed to high-speed.
: Data & clock recovery circuit
: Downstream Port Controller handles Port Reset, Enable, Disable, Suspend and
Resume
: Downstream transceiver supports high-speed (480 Mbps), full-speed (12 Mbps), and
low-speed (1.5 Mbps) transaction
: Endpoint 0 controller
: Endpoint 1 controller
: Manages hub’s synchronization by using micro-SOF which is received at upstream
port, and generates SOF packet when full/low-speed device is attached to
downstream facing port.
: Full/low-speed repeater is enabled when the
μ
PD720114 are worked at full-speed
mode
: Oscillator Block
: On chip 2.5V regulator
: Serializer and Deserializer
: Serial Interface Engine (SIE) controls USB2.0 and 1.1 protocol sequencer.
: Upstream Transceiver supports high-speed (480 Mbps), full-speed (12 Mbps)
transaction
: Upstream Port Controller handles Suspend and Resume
CDR
DPC
DP(n)_PHY
EP0
EP1
F_TIM (Frame Timer)
FS_REP
OSB
2.5V REG
SERDES
SIE_2H
UP_PHY
UPC
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