參數(shù)資料
型號(hào): uPD720114GA-YEU-A
廠商: NEC Corp.
英文描述: MOS INTEGRATED CIRCUIT
中文描述: 馬鞍山集成電路
文件頁(yè)數(shù): 18/32頁(yè)
文件大?。?/td> 269K
代理商: UPD720114GA-YEU-A
Data Sheet S17462EJ4V0DS
18
μ
PD720114
USB Interface Block
(1/4)
Parameter
Symbol
Conditions
Min.
Max.
Unit
Low-speed Electrical Characteristics
Rise time (10% to 90%)
t
LR
C
L
= 200 pF to 600 pF
75
300
ns
Fall time (90% to 10%)
t
LF
C
L
= 200 pF to 600 pF
75
300
ns
Differential rise and fall time matching
t
LRFM
(t
LR
/t
LF
)
Note
80
125
%
Low-speed data rate
t
LDRATHS
Average bit rate
1.49925
1.50075
Mbps
Downstream facing port source jitter total
(including frequency tolerance) (
Figure
2-13
):
To next transition
For paired transitions
t
DDJ1
t
DDJ2
25
14
+
25
+
14
ns
ns
Downstream facing port differential receiver
jitter total (including frequency tolerance)
(
Figure 2-15
):
To next transition
For paired transitions
t
UJR1
t
UJR2
152
200
+
152
+
200
ns
ns
Source SE0 interval of EOP (
Figure 2-14
)
t
LEOPT
1.25
1.5
μ
s
Receiver SE0 interval of EOP (
Figure 2-14
)
t
LEOPR
670
ns
Width of SE0 interval during differential
transition
t
LST
210
ns
Hub differential data delay (
Figure 2-11
)
t
LHDD
300
ns
Hub differential driver jitter (including cable)
(
Figure 2-11
):
Downstream facing port
To next transition
For paired transitions
Upstream facing port
To next transition
For paired transitions
t
LDHJ1
t
LDHJ2
t
LUHJ1
t
LUHJ2
45
15
45
45
+
45
+
15
+
45
+
45
ns
ns
ns
ns
Data bit width distortion after SOP (
Figure
2-11
)
t
LSOP
60
+
60
ns
Hub EOP delay relative to t
HDD
(
Figure 2-12
)
t
LEOPD
0
200
ns
Hub EOP output width skew (
Figure 2-12
)
t
LHESK
300
+
300
ns
Full-speed Electrical Characteristics
Rise time (10% to 90%)
t
FR
C
L
= 50 pF,
R
S
= 36
Ω
4
20
ns
Fall time (90% to 10%)
t
FF
C
L
= 50 pF,
R
S
= 36
Ω
4
20
ns
Differential rise and fall time matching
t
FRFM
(t
FR
/t
FF
)
90
111.11
%
Full-speed data rate
t
FDRATHS
Average bit rate
11.9940
12.0060
Mbps
Frame interval
t
FRAME
0.9995
1.0005
ms
Note
Excluding the first transition from the Idle state.
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