IEEE1394 400Mbps PHY
DATA SHEET
MOS INTEGRATED CIRCUIT
μ
PD72850A
Document No. S14452EJ1V0DS00 (1st edition)
Date Published October 1999 NS CP(K)
Printed in Japan
1999
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
The
μ
PD72850A is the 3-port physical layer LSI which complies with the P1394a draft 2.0 specifications.
The
μ
PD72850A works up to 400 Mbps. It is an upgrade of NEC's
μ
PD72850.
FEATURES
The Three-port Physical Layer LSI complies to IEEE P1394a draft 2.0
Connection debounce
Arbitration enhancements
Arbitrated short bus reset
Ack-accelerated arbitration
Fly-by concatenation
Multiple-speed packet concatenation
Arbitration enhancements and cycle start (controlled by the Link layer)
Performance optimization via PHY pinging
Priority arbitration (controlled by the Link layer)
Data rate: 393.216 / 196.608 / 98.304 Mbps
Compliant with Suspend/Resume function as defined in P1394a draft 2.1
3.3 V single power supply
Electrical isolated Link interface
24.576 MHz crystal clock generation, 393.216 MHz PLL multiplying frequency
System power management by signaling of node power class information
Cable power monitor (CPS) is equipped
Fully interoperable with IEEE1394 std 1394 Link (FireWire
TM
, i.LINK
TM
)
Cable bias and terminal voltage driver supply function (for 3-port each)
Separate digital power and analog GND
Enable/Disable port control switch when power supply is powered on
Support Suspend/Resume Off mode (Compliant with P1394a draft 1.3)
Number of supported port are selectable
1port, 2port, 3port. This selection is only under Suspend/Resume Off mode
Compliant with MD8405E (FUJIFILM MICRODEVICES CO., LTD)
ORDERING INFORMATION
Part number Package
μ
PD72850AGK-9EU 80-pin plastic TQFP (Fine pitch) (12 x 12 mm)