參數(shù)資料
型號: UPD72850A
廠商: NEC Corp.
英文描述: IEEE1394 400Mbps PHY
中文描述: IEEE1394連接400Mbps的物理層
文件頁數(shù): 21/48頁
文件大?。?/td> 290K
代理商: UPD72850A
Data Sheet S14452EJ1V0DS00
21
μ
PD72850A
4. PHY/LINK INTERFACE
4.1 Initialization of Link Power Status (LPS) and PHY/Link Interface
The LPS pin monitors the On/Off status of the Link power state. This pin is used during the PHY/Link interface
Enable/Disable (initialization).
Reset
When the LPS input pin is Low for TLPS_RESET:
CTL0,CTL1 and D0-D7 output Low (When the isolation barrier is Hi-Z).
SCLK continuously supplies the clock signal to the Link.
Disable
When the LPS input pin is Low for TLPS_DISABLE:
CTL0,CTL1, D0-D7 continue to output Low as TLPS_RESET has already occurred (When the isolation barrier is Hi-Z).
SCLK to Link stops and it outputs Low (When the isolation barrier is Hi-Z).
Table 4-1. LPS Timing Parameters
Parameter
Symbol
MIN.
MAX.
Unit
LPS = Low propagation delay (with isolation barrier)
t
LPSL
0.09
1.00
μ
s
LPS = High propagation delay (with isolation barrier)
t
LPSH
0.09
1.00
μ
s
Reset active
t
LPS_RESET
1.2
2.75
μ
s
Disable active
t
LPS_DISABLE
25
30
μ
s
Setup time when using isolation barrier
t
RESTORE
15
20
μ
s
Figure 4-1. LPS Waveform when Connected to Isolation Barrier
t
LPSH
t
LPSL
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