- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄376430 > UPD72850A (NEC Corp.) IEEE1394 400Mbps PHY PDF資料下載
參數(shù)資料
| 型號(hào)： | UPD72850A |
| 廠商： | NEC Corp. |
| 英文描述： | IEEE1394 400Mbps PHY |
| 中文描述： | IEEE1394連接400Mbps的物理層 |
| 文件頁(yè)數(shù)： | 30/48頁(yè) |
| 文件大?。?/td> | 290K |
| 代理商： | UPD72850A |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)當(dāng)前第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)
Data Sheet S14452EJ1V0DS00
30
μ
PD72850A
4.6 Transmit
The
μ
PD72850A arbitrates the serial bus using Link’s LREQ.
When the
μ
PD72850A acquires the bus, a Grant period of 1 SCLK is executed to CTL0,CTL1. After that, an Idle
period of 1 SCLK cycle is executed.
Link controls the interface executing Idle, Hold of Transmit to CTL0,CTL1 after 1 SCLK cycle when Grant from
PHY is detected.
Before asserting Hold and Transmit, assert 1 Idle cycle. Do not execute Idle for 2 or more cycles.
If the packet transmit is not ready, the Hold period can be extended up to MAX_HOLD.
The
μ
PD72850A outputs DATA_PREFIX to the serial bus while Hold is being asserted to CTL.
When the packet transmit is ready, Link outputs the first bit of the packet and Transmit is asserted to CTL at the
same time.
After transmitting the last bit of the packet, Link outputs for Idle or Hold to CTL for 1 cycle. After that, it outputs
Idle for 1 cycle.
When PHY/Link releases the bus, output Low to CTL and D0-D7 within 1 cycle.
Figure 4-6. Transmit Timing
00
11
00
ZZ
ZZ
ZZ
ZZ
ZZ
ZZ
ZZ
ZZ
ZZ
00
00
00
00
ZZ
ZZ
ZZ
ZZ
ZZ
ZZ
ZZ
ZZ
ZZ
00
ZZ
ZZ
ZZ
00
01
01
10
10
10
10
00
00
ZZ
ZZ
ZZ
ZZ
00
00
00
D0
D1
D2
D
n
00
00
ZZ
ZZ
ZZ
ZZ
ZZ
00
00
11
00
ZZ
ZZ
ZZ
ZZ
ZZ
ZZ
ZZ
00
00
00
00
ZZ
ZZ
ZZ
10
10
01
00
ZZ
ZZ
ZZ
ZZ
01
10
10
D
n-1
D
n
SP
00
ZZ
ZZ
ZZ
ZZ
00
D0
D1
ZZ
ZZ
01
00
(a) Single Packet
PHY CTL0,CTL1
PHY D0-D7
Link CTL0,CTL1
Link D0-D7
(b) Concatenated Packet
PHY CTL0,CTL1
PHY D0-D7
Link CTL0,CTL1
Link D0-D7
ZZ
ZZ
00
00
Note
In case of packet transmission after Grant, before actual transmission, Hold does not need to be asserted.
Link can transmit continuous packets without releasing the bus.
Hold is asserted to CTL. This function is used when the Link transmits continuous packets after acknowledge and
isochronous packets. Link outputs the transfer rate signal of the following packet to D0-D7 and asserts Hold
simultaneously.
After Hold is detected by MIN_PACKET_SEPARATION, the
μ
PD72850A outputs Grant to CTL.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| UPD72850AGK-9EU | Circular Connector; No. of Contacts:56; Series:MS27467; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:25; Circular Contact Gender:Pin; Circular Shell Style:Straight Plug; Insert Arrangement:25-4 RoHS Compliant: No |
| uPD750066CU | 4-BIT SINGLE-CHIP MICROCONTROLLERS |
| uPD750068GT | 4-BIT SINGLE-CHIP MICROCONTROLLERS |
| uPD750068GTA | 4-BIT SINGLE-CHIP MICROCONTROLLERS |
| uPD750066GTA | CONNECTOR ACCESSORY |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UPD74HC04C | 制造商:Panasonic Industrial Company 功能描述:IC |
| UPD750068GT-396 | 制造商:Renesas Electronics Corporation 功能描述: |
| UPD7507C189 | 制造商:Panasonic Industrial Company 功能描述:IC |
| UPD7508CU265 | 制造商:Panasonic Industrial Company 功能描述:IC |
| UPD75208 | 制造商:Panasonic Industrial Company 功能描述:IC |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。