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參數(shù)資料
| 型號： | UPD72850A |
| 廠商： | NEC Corp. |
| 英文描述： | IEEE1394 400Mbps PHY |
| 中文描述： | IEEE1394連接400Mbps的物理層 |
| 文件頁數(shù)： | 23/48頁 |
| 文件大?。?/td> | 290K |
| 代理商： | UPD72850A |
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Data Sheet S14452EJ1V0DS00
23
μ
PD72850A
The
μ
PD72850A activates the PHY/Link interface when LPS is 1, regardless of the value of the Link active bit.
4.3 PHY/Link Interface Operation (CTL0, CTL1, LREQ, D0-D7)
The PHY/Link Interface consists of the following operations:
Status transfer to the Link layer controller by CTL
Transmit packet
Receive packet
Request from the Link layer controller by LREQ
4.3.1 CTL0,CTL1
CTL0,CTL1 controls the PHY/Link interface as shown in the Table 4-3.
Table 4-3. CTL Controls PHY
CTL0,CTL1
Type
Content
00
Idle
PHY is in idle function
01
Status
PHY transmitting status information to Link
10
Receive
PHY receiving data from the Link
11
Grant
PHY allows Link to transmit data
This is the operation by which, after Grant, the Link obtains the right to control the interface.
Table 4-4. CTL Controls Link
CTL0,CTL1
Type
Content
00
Idle
Link completes the packet transmission and releases the PHY/Link interface.
01
Hold
1) Link transmits Hold until the data is ready for transmission.
2) Link transmits the interface connect packet.
10
Transmit
Link transmits the data to PHY.
11
-
Not used.
4.3.2 LREQ
Access to the PHY register and the bus is controlled from the Link layer controller through the LREQ pin of PHY.
Figure 4-3. LREQ and CTL Timing
LR0
LR1
LR2
LR3
LR
(n-2)
LR
(n-1)
C
A
C
B
LREQ
CTL0,CTL1
C
A
: CTL before generation of LREQ
C
B
: CTL during LREQ execution
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