參數(shù)資料
型號: uPD720114GA-YEU-A
廠商: NEC Corp.
英文描述: MOS INTEGRATED CIRCUIT
中文描述: 馬鞍山集成電路
文件頁數(shù): 12/32頁
文件大?。?/td> 269K
代理商: UPD720114GA-YEU-A
Data Sheet S17462EJ4V0DS
12
μ
PD720114
USB Interface Block
Parameter
Symbol
Conditions
Min.
Max.
Unit
Output pin impedance
Z
HSDRV
Includes R
S
resistor
40.5
49.5
Ω
Termination voltage for upstream facing
port pullup (full-speed)
V
TERM
3.0
3.6
V
Input Levels for Low-/full-speed:
High-level input voltage (drive)
V
IH
2.0
V
High-level input voltage (floating)
V
IHZ
2.7
3.6
V
Low-level input voltage
V
IL
0.8
V
Differential input sensitivity
V
DI
(D
+
)
(D
)
0.2
V
Differential common mode range
V
CM
Includes V
DI
range
0.8
2.5
V
Output Levels for Low-/full-speed:
High-level output voltage
V
OH
R
L
of 14.25 k
Ω
to GND
2.8
3.6
V
Low-level output voltage
V
OL
R
L
of 1.425 k
Ω
to 3.6 V
0.0
0.3
V
SE1
V
OSE1
0.8
V
Output signal crossover point voltage
V
CRS
1.3
2.0
V
Input Levels for High-speed:
High-speed squelch detection threshold
(differential signal)
V
HSSQ
100
150
mV
High-speed disconnect detection
threshold (differential signal)
V
HSDSC
525
625
mV
High-speed data signaling common
mode voltage range
V
HSCM
50
+
500
mV
High-speed differential input signaling
levels
See
Figure 2-4
.
Output Levels for High-speed:
High-speed idle state
V
HSOI
10.0
+
10
mV
High-speed data signaling high
V
HSOH
360
440
mV
High-speed data signaling low
V
HSOL
10.0
+
10
mV
Chirp J level (different signal)
V
CHIRPJ
700
1100
mV
Chirp K level (different signal)
V
CHIRPK
900
500
mV
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