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參數(shù)資料
| 型號： | UCB1500 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI to AC97 bridge/host controller |
| 中文描述： | PCI BUS CONTROLLER, PQFP80 |
| 封裝： | 12 X 12 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-315-1, LQFP-80 |
| 文件頁數(shù)： | 39/58頁 |
| 文件大?。?/td> | 1001K |
| 代理商： | UCB1500 |
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Philips Semiconductors
UCB1500
PCI to AC97 bridge/host controller
Objective specification
Rev. 01 — 4 February 2000
39 of 58
9397 750 06854
Philips Electronics N.V. 2000. All rights reserved.
8.6.17
[00d5] Miscellaneous AC97 control/status register (V
DD
powered)
8.6.18
[d6]: Reserved
8.6.19
[d7]: AC97 semaphore register
Table 59: Miscellaneous AC97 control/status register bit description
V
DD
powered.
Bit
Description
15-9
Reserved.
8
Merge DIN[1:0]
Must be set to 1. Data coming in on channel #0 and channel #1 will be combined
into 1 channel. Codec ready and resume event detection will still be detected
separately.
7-5(r)
Power down SYNC counter
Number of SYNCs since BITCLK is stopped and SYNC is “0”. This number
increments after each
PCICLK
4096
time period.
4
Shutdown AC Link
Default = 0. Writing “1” to this register shall cause UCB1500 to disable AC Link
signals (SYNC and SDATA_OUT to 0). Writing “0” shall enable normal AC Link
operation.
3
Channel #1 Codec Ready status
This bit reflects the Codec Ready bit of AC97 Channel #1.
2
Channel #0 Codec Ready status
This bit reflects the Codec Ready bit of AC97 Channel #0.
1-0
Reserved.
Table 60: AC97 semaphore register bit description
Bit
Description
15-12
Reserved.
11-1
Reserved.
0
Semaphore bit
Reads will return the current value, then set the bit to 1. Writing a “1” to this bit
will clear it.
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相關代理商/技術參數(shù) |
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