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參數資料
| 型號： | UCB1500 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI to AC97 bridge/host controller |
| 中文描述： | PCI BUS CONTROLLER, PQFP80 |
| 封裝： | 12 X 12 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-315-1, LQFP-80 |
| 文件頁數： | 24/58頁 |
| 文件大?。?/td> | 1001K |
| 代理商： | UCB1500 |
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Philips Semiconductors
UCB1500
PCI to AC97 bridge/host controller
Objective specification
Rev. 01 — 4 February 2000
24 of 58
9397 750 06854
Philips Electronics N.V. 2000. All rights reserved.
8.1.9
[0018-0019] Receive DMA #0 descriptor table pointer (DTP)
8.1.10
[001a]: Receive DMA #0 FIFO count register.
8.1.11
[001b]: Receive DMA #0 command register
Similar to Receive DMA #1 command register.
8.1.12
[001c-001d]: Transmit DMA #0 descriptor table pointer(DTP)
8.1.13
[001e]: Transmit DMA #0 FIFO counter register
8.1.14
[001f]: Transmit DMA #0 command register
Similar to Transmit DMA #1 command register
8.1.15
[0020 - 002F] Reserved
8.1.16
[0030]: Receive DMA #1 Byte Counter
4(w)
Immediate Transmit Abort
Set this bit to immediately abort the current block trans mission. The fifo will also
be flushed. A partial initialization will be required to resume the transmission.
After setting this bit to 1, set bit 5 of this register, then clear this bit. See abort
procedures for more details.
Abort status
PCI aborted, or Software aborted, or DMA underrun = 1.
Normal Transmit Abort
Set this bit to abort the current block transmission after the current data buffer
has been completely transmitted. The FIFO will also be flushed. A partial
initialization will be required to resume the transmission. After setting this bit to 1,
set bit 5 of this register, then clear this bit. See abort procedures for more details
Start transmit-DMA #1
Set this bit to initiate DMA#1 transmit mode after the transmit descriptor tables
are ready.
HOLD status/acknowledge
If this bit is set upon a read access, the UCB1500 is currently in the hold
condition, as a result of reading an invalid descriptor entry, and is waiting for an
acknowledgment before proceeding. Writing a ‘1’ to this bit will send a hold
acknowledge to the UCB1500.
Reserved.
4(r)
3
2(w)
1
0
Table 29: Transmit DMA #1 Command Register bit description
…continued
Bit
Description
Table 30: Receive DMA #1 Byte Counter register bit description
Bit
Description
15-0
Receive DMA #1 Byte Counter
Number of valid bytes in the data buffer pointed to by receive DMA #1 current
descriptor entry. This counter counts up from 0 and contains the number of bytes
received and transferred to memory.
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