參數(shù)資料
型號(hào)： UCB1500
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： PCI to AC97 bridge/host controller
中文描述： PCI BUS CONTROLLER, PQFP80
封裝： 12 X 12 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-315-1, LQFP-80
文件頁(yè)數(shù)： 22/58頁(yè)
文件大?。?/td> 1001K
代理商： UCB1500
Philips Semiconductors
UCB1500
PCI to AC97 bridge/host controller
Objective specification
Rev. 01 — 4 February 2000
22 of 58
9397 750 06854
Philips Electronics N.V. 2000. All rights reserved.
8.1.6
[0014-0015]: Transmit DMA #1 descriptor table pointer (DTP).
[0014] lower 16-bit of DTP
[0015] higher 16-bit of DTP
11(r)
Receive DMA #1 DT full
This read-only bit is set whenever all the receive descriptors for DMA #1 have
been used, and the receive DMA is done. If descriptor table is setup as a circular
queue, this bit does not become set. Writing a ‘1’ to this register clears this
status bit.
Reserved.
Receive-DMA #1 active status
If set, DT of receive DMA #1 is currently receiving data.
Receive DMA #1 enable
Must be set to 1.
Reserved.
Receive DMA #1 clear abort
Setting this bit clears the receive abort condition. This also clears bit 12 of this
register.
Receive DMA #1 software abort
Setting this bit immediately aborts receive cycle and disables receive DMA #1.
This also causes bit 12 of this register to become set.
Reserved.
Start receive-DMA #1
Set this bit to 1 initiate DMA#1 receive mode after the receive descriptor tables
are setup.
HOLD status/acknowledge
If this bit is set upon a read access, the UCB1500 is currently in the hold
condition, as a result of reading an invalid descriptor entry, and is waiting for an
acknowledgment before proceeding. Writing a 1 to this bit will send a hold
acknowledge to the UCB1500.
Reserved.
10-9
8(r)
7
6
5(w)
4(w)
3
2(w)
1
0
Table 27: Receive DMA #1 Command Register bit description
…continued
Bit
Description
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