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參數(shù)資料
| 型號： | UCB1500 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI to AC97 bridge/host controller |
| 中文描述： | PCI BUS CONTROLLER, PQFP80 |
| 封裝： | 12 X 12 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-315-1, LQFP-80 |
| 文件頁數(shù)： | 28/58頁 |
| 文件大小： | 1001K |
| 代理商： | UCB1500 |
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Philips Semiconductors
UCB1500
PCI to AC97 bridge/host controller
Objective specification
Rev. 01 — 4 February 2000
28 of 58
9397 750 06854
Philips Electronics N.V. 2000. All rights reserved.
8.2.3
[005a]: Host interrupt status-register #1
8.2.4
[005b]: Host interrupt status-register #2
8.2.5
[005c]: Reserved
Should
NEVER
be accessed (read or written).
8.2.6
[005d]: Reserved
8.2.7
[005e]: Host interrupt enable #3
Table 38: Host interrupt status-register bit description
Bit
Description
15(r)
Logical OR of register 5b.
14-12(r)
Reserved.
11(r)
Transmit DMA #1 DT done/Hold
10-9
Reserved.
8(r)
Receive DMA #1 DT done/Hold
7-3
Reserved.
2(r)
Receive DMA #1 done
1-0(r)
Reserved.
Table 39: Host interrupt status-register #2 bit description
Bit
Description
15-6
Reserved.
5(r)
Transmit DMA #1 Error
4-3
Reserved.
2(r)
Receive DMA #1 Error
1-0
Reserved.
Table 40: Host interrupt enable #3 register bit description
Bit
Description
15
Transmit DMA #0 done
If set, interrupt will occur after DMA portion of transmit cycle is done. Part of the
frame may still be in the internal FIFO, and not yet transmitted.
14
Transmit DMA #1 done
13-12
Reserved.
11
Counter #0 interrupt
10
Counter #1 interrupt
9-7
Reserved.
5
Transmit DMA #0 error
4
Receive DMA #0 error
3
Transmit DMA #0 DT done/Hold
2
Receive DMA #0 DT done/Hold
1
Reserved.
0
Receive DMA #0 done
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