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參數(shù)資料
| 型號： | UCB1500 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI to AC97 bridge/host controller |
| 中文描述： | PCI BUS CONTROLLER, PQFP80 |
| 封裝： | 12 X 12 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-315-1, LQFP-80 |
| 文件頁數(shù)： | 27/58頁 |
| 文件大?。?/td> | 1001K |
| 代理商： | UCB1500 |
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Philips Semiconductors
UCB1500
PCI to AC97 bridge/host controller
Objective specification
Rev. 01 — 4 February 2000
27 of 58
9397 750 06854
Philips Electronics N.V. 2000. All rights reserved.
8.2 Interrupt Controller Registers
Note:
Interrupt status can also be read by accessing the status port 1.
When UCB1500 generates an interrupt, first interrupt blocks the subsequent
interrupts. Thus, when the interrupt routine acknowledges the interrupt, only the
first sequence of interrupt event gets cleared. The UCB1500 would then generate
another interrupt to account for the subsequent events, which will then be cleared
by the next acknowledge from the interrupt service routine.
8.2.1
[0058]: Host interrupt enable #1
8.2.2
[0059]: Host interrupt enable #2
Table 36: Host interrupt enable #1 register bit description
Bit
Description
15-12
Reserved.
11
Transmit DMA #1 DT done/Hold
If set, an interrupt will occur whenever the current DMA #1 transmit DT has been
fully utilized. Also, an interrupt will occur when a hold condition takes place.
10-9
Reserved.
8
Receive DMA #1 DT done/Hold
If set, an interrupt will occur if the current receive DMA #1 DT is full. Interrupt
occurs after all the data area is filled in the current DT and after all the current DT
entries status have been updated. Also, an interrupt will occur when a hold
condition takes place.
7-3
Reserved.
2
Receive DMA #1 DMA done
:
If set, an interrupt will occur after every received block on DMA # 1 receive
channel. Interrupt occurs after all the current DT entry data area is filled and
after the current DT entry status has been updated. Each DT entry can only have
one frame or part of a frame in it. Each new frame will require a new DT entry.
1-0
Reserved.
Table 37: Host interrupt enable #2 register bit description
Bit
Description
15-6
Reserved.
5
Transmit DMA #1 Error
If set, an interrupt will occur if the transmit DMA #1 causes a transmit buffer
underrun by not servicing a transmit buffer fetch request.
4-3
Reserved.
2
Receive DMA #1 Error
If set, an interrupt will occur if the receive DMA #1 is overrun.
1-0
Reserved.
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