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參數(shù)資料
| 型號： | TSXPC603RCA10LC |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 233 MHz, RISC PROCESSOR, CQFP240 |
| 封裝： | CAVITY UP, CERQUAD-240 |
| 文件頁數(shù)： | 9/40頁 |
| 文件大?。?/td> | 670K |
| 代理商： | TSXPC603RCA10LC |
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TSPC603r
in CERQUAD and MQUAD Packages
17/40
4.3. Dynamic characteristics
4.3.1. Clock AC specifications
Table 9 provides the clock AC timing specifications as defined in Figure 4.
Table 9.Clock AC timing specifications
Vdd = AVdd = 2.5 V
± 5 % ; OVdd = 3.3 ± 5 % V dc, GND = 0 V dc, –55°C ≤ TC ≤ 125°C
Num
Characteristics
166 MHz
200 MHz
Unit
Note
Min
Max
Min
Max
Processor frequency
150
166
150
200
MHz
5
VCO frequency
300
332
300
400
MHz
5
SYSCLK (bus) frequency
25
66.7
33.3
66.7
MHz
5
1
SYSCLK cycle time
15
30
13.3
30
ns
2,3
SYSCLK rise and fall time
–
2.0
–
2.0
ns
1
4
SYSCLK duty cycle (1.4V mea-
sured)
40.0
60.0
40.0
60.0
%
3
SYSCLK jitter
–
±150
–
±150
ps
2
603r internal PLL relock time
–
100
–
100
ms
3,4
Notes:
1. Rise and fall times for the SYSCLK input are measured from 0.4 V to 2.4 V.
2. Cycle-to-cycle jitter is guaranteed by design.
3. Timing is guaranteed by design and characterization, and is not tested.
4. PLL relock time is the maximum amount of time required for PLL lock after a stable Vdd, OVdd, AVdd and SYSCLK are reached during the
power-onreset sequence. This specification also applies when the PLL has been disabled and subsequently re-enabled during sleep mode.
Also note that HRESET must be held asserted for a minimum of 255 bus clocks after the PLL relock time (100
ms) during the power-on reset
sequence.
5. Caution: The SYSCLK frequency and PLL_CFG[0–3] settings must be chosen such that the resulting SYSCLK (bus) frequency, CPU (core)
frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum operating frequencies. Refer to the PLL_CFG[0–3]
signal description for valid PLL_CFG[0–3] settings.
Figure 4 : SYSCLK input timing diagram
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